Readout circuitry for photomultiplier and photomultiplier
AssigneeTarget Systemelektronik GmbH & Co. KG
InventorJürgen Stein
Life of this patent
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Abstract
Readout circuitry for a PMT is provided, which is adapted for delivering a pair of first and second synchronous output voltage signals to a pair of outputs, the first output signal of the pair having a first AC portion being representative of a charge flow of an anode of the PMT over time, the second output signal of the pair having a second AC portion which corresponds to an inverted form of the first AC portion of the first output signal. The readout circuitry comprises a first sub-circuitry which is adapted to derive the first output signal from the charge flow over time of the anode, and a second sub-circuitry which is adapted to derive the second output signal from a charge flow over time of at least one dynode of the PMT.
Claims27
Readout circuitry for a PMT, which is adapted for providing a pair of first and second synchronous output signals (UA out+, UA out−), the first output signal (UA out+) of the pair having a first AC portion being representative of a charge flow of an anode (AN) of the PMT over time, the second output signal (UA out−) of the pair having a second AC portion which corresponds to an inverted form of the first AC portion of the first output signal (UA out+), the readout circuitry comprising:
- a first sub-circuitry (RAH, RAL) which is adapted to derive the first output signal (UA out+) from the charge flow over time (iA) of the anode (AN), and
- a second sub-circuitry (RDH+RDL) which is adapted to derive the second output signal (UA out−) from a charge flow over time (iD) of at least one dynode (DN, DN-1, DN-2, . . . ) of the PMT,
- wherein the first output signal further comprises a first DC portion (UCENTER+UMAX/2) and the second output signal further comprises a second DC portion (UCENTER−UMAX/2),
- wherein the first sub-circuitry comprises a first voltage source circuit (VDD) for setting the first DC portion of the first output signal (UA out+) and the second sub-circuitry comprises a second voltage source circuit (VDD) for setting the second DC portion of the second output signal (UA out−),
- wherein the first sub-circuitry comprises first and second resistor elements, for setting the DC portion of the first output signal (UA out+), and the second sub-circuitry comprises third and fourth resistor elements, for setting DC portion of the second output voltage (UA out−).
Dependencies are inferred from the claim text.