Reconfigurable scan network defect diagnosis
AssigneeMentor Graphics Corporation
InventorsGivargis Avareh Danialy, Martin Keim
Life of this patent
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Abstract
A reconfigurable scan network in a circuit is configured such that a first scan path is used if a programmable component has no stuck-at fault and a second scan path is used if the programmable component has a stuck-at fault. A test pattern having a length equal to a length of the second path is shifted into the reconfigurable scan network, and a part or a whole of the test pattern is then shifted out from the reconfigurable scan network. The part or the whole of the test pattern being shifted out is analyzed to determine whether the programmable component has the stuck-at fault.
Claims15
A method, comprising:
- configuring a reconfigurable scan network in a circuit such that a first scan path is used if a programmable component has no stuck-at fault and a second scan path is used if the programmable component has a stuck-at fault, the first scan path and the second scan path sharing a same scan path segment after the programmable component;
- shifting a test pattern having a length equal to a length of the second path into the reconfigurable scan network;
- shifting out a part or a whole of the test pattern from the reconfigurable scan network;
- and
- analyzing the part or the whole of the test pattern being shifted out to determine whether the programmable component has the stuck-at fault, the analyzing comprises:
- determining whether the part or the whole of the test pattern is shifted out at clock cycles expected for the second scan path.
One or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors to perform a method, the method comprising:
- generating configuration data for configuring a reconfigurable scan network in a circuit such that a first scan path is used if a programmable component has no stuck-at fault and a second scan path is used if the programmable component has a stuck-at fault, the first scan path and the second scan path sharing a same scan path segment after the programmable component;
- and
- generating a test pattern having a length equal to a length of the second path for being shifting into and out from the reconfigurable scan network configured by the configuration data, wherein a part or a whole of the test pattern being shifted out is analyzed to determine whether the programmable component has the stuck-at fault, the analyzing comprises:
- determining whether the part or the whole of the test pattern is shifted out at clock cycles expected for the second scan path.
A method, executed by at least one processor of a computer, comprising:
- generating configuration data for configuring a reconfigurable scan network in a circuit such that a first scan path is used if a programmable component has no stuck-at fault and a second scan path is used if the programmable component has a stuck-at fault, the first scan path and the second scan path sharing a same scan path segment after the programmable component;
- and
- generating a test pattern having a length equal to a length of the second path for being shifting into and out from the reconfigurable scan network configured by the configuration data, wherein a part or a whole of the test pattern being shifted out is analyzed to determine whether the programmable component has the stuck-at fault, the analyzing comprises:
- determining whether the part or the whole of the test pattern is shifted out at clock cycles expected for the second scan path.
Dependencies are inferred from the claim text.