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US 10,517,471 B2Granted
Pixel array area optimization using stacking scheme for hybrid image sensor with minimal vertical interconnects
AssigneeDePuy Synthes Products, Inc.
InventorLaurent Blanquart
Life of this patent
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Abstract
Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed.
Claims18
An imaging sensor comprising:
- a plurality of stacked substrates comprising a first substrate and one or more additional substrates;
- a pixel array comprising a plurality of pixel columns located on the first substrate, wherein the pixel array receives and converts electromagnetic energy to data or data signals, wherein the pixel array covers a majority of the first substrate;
- supporting circuits for processing the data or data signals positioned on the one or more additional substrates, wherein the supporting circuits are divided into circuit columns corresponding to each pixel column;
- and
- a plurality of pixel column buses positioned on the first substrate and a plurality of circuit column buses on the one or more additional substrates to communicate the data or the data signals from the pixel array to the one or more additional substrates,
- a plurality of interconnects between the first substrate and the one or more additional substrates, wherein at least one interconnect provides an electrical communication between one pixel column bus and one corresponding circuit column bus;
- wherein at least a portion of each of the plurality of pixel column buses is superimposed with at least a portion of each of the corresponding plurality of circuit column buses, wherein said at least one interconnect is located anywhere along the superimposition of one pixel column bus and one corresponding circuit column bus.
4 more elements
An imaging sensor comprising:
- a plurality of stacked substrates comprising a first substrate and one or more additional substrates;
- a pixel array comprising a plurality of pixel columns located on the first substrate, wherein the pixel array receives and converts electromagnetic energy to data or data signals;
- supporting circuits for processing the data or data signals positioned on the one or more additional substrates, wherein the supporting circuits are divided into circuit columns corresponding to each pixel column;
- a plurality of pixel column buses positioned on the first substrate and a plurality of circuit column buses on the one or more additional substrates to communicate the data or the data signals from the pixel array to the one or more additional substrates;
- a second pixel array laterally offset from the first pixel array for three-dimensional image capture;
- a plurality of interconnects between the first substrate and the one or more additional substrates, wherein at least one interconnect provides an electrical communication between one pixel column bus and one corresponding circuit column bus;
- wherein at least a portion of each of the plurality of pixel column buses is superimposed with at least a portion of each of the corresponding plurality of circuit column buses, wherein said at least one interconnect is located anywhere along the superimposition of one pixel column bus and one corresponding circuit column bus.
4 more elements
An imaging sensor comprising:
- a plurality of stacked substrates comprising a first substrate and one or more additional substrates;
- a pixel array comprising a plurality of pixel columns located on the first substrate, wherein the pixel array receives and converts electromagnetic energy to data or data signals, wherein the pixel array covers a majority of the first substrate;
- supporting circuits for processing the data or data signals positioned on the one or more additional substrates, wherein the supporting circuits are divided into circuit columns corresponding to each pixel column;
- and
- a plurality of pixel column buses positioned on the first substrate and a plurality of circuit column buses on the one or more additional substrates to communicate the data or the data signals from the pixel array to the one or more additional substrates;
- wherein at least one of the one or more additional substrates comprises a second substrate with a protruding portion, wherein the protruding portion extends beyond an edge of a neighboring substrate,
- a plurality of interconnects between the first substrate and the second substrate, wherein at least one interconnect provides an electrical communication between one pixel column bus and one corresponding circuit column bus;
- wherein at least a portion of each of the plurality of pixel column buses is superimposed with at least a portion of each of the corresponding plurality of circuit column buses, wherein said at least one interconnect is located anywhere along the superimposition of one pixel column bus and one corresponding circuit column bus.
5 more elements
Dependencies are inferred from the claim text.