# US 10,515,567 B2 · Cryptographic machines with N-state lab-transformed switching devices

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- Number: US 10,515,567 B2
- Document ID: US10515567B2
- Status: Granted
- Kind: B2
- Application number: 15/442,556
- Filed: 2017-02-24
- Published: 2017-06-15
- Granted: 2019-12-24
- Earliest claimed: 2010-06-01
- Assignees: Ternarylogic LLC
- Applicants: Peter Lablans
- Inventors: Peter Lablans
- Web page: https://patentgrep.com/patent/US10515567B2

## CPC

- G09C 1/00: Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00)
- G06F 5/012: {in floating-point computations}
- G06F 7/4876: {Multiplying}
- G06F 7/724: {Finite field arithmetic (for error detection or correction in general H03M13/00, in computers G06F11/10)}
- G06Q 20/40975: {using encryption therefor}
- H03M 7/00: Conversion of a code where information is represented by a given sequence or number of digits to a code where the same {, similar or subset of} information is represented by a different sequence or number of digits
- H04L 9/0643: {Hash functions, e.g. MD5, SHA, HMAC or f9 MAC}
- H04L 9/0841: {involving Diffie-Hellman or related key agreement protocols}
- H04L 9/14: using a plurality of keys or algorithms
- H04L 9/3013: {involving the discrete logarithm problem, e.g. ElGamal or Diffie-Hellman systems}
- H04L 9/302: {involving the integer factorization problem, e.g. RSA or quadratic sieve [QS] schemes}
- H04L 9/3066: {involving algebraic varieties, e.g. elliptic or hyper-elliptic curves}
- H03M 13/1102: {Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes}
- H03M 13/1515: {Reed-Solomon codes}
- H03M 13/23: using convolutional codes, e.g. unit memory codes
- H04L 2209/12: Details relating to cryptographic hardware or logic circuitry
- G09C: CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06Q: INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

N-state switching tables are transformed by a Lab-transform into a Lab-transformed n-state switching table. Memory devices, processors and combinational circuits with inputs and an output are characterized by the Lab-transformed n-state switching table and perform switching operations between physical states in accordance with a Lab-transformed n-state switching table. The devices characterized by Lab-transformed n-state switching tables are applied in cryptographic devices. The cryptographic devices perform standard cryptographic operations that are modified in accordance with a Lab-transform.

## Claims

### Claim 1

A cryptographic apparatus to modify one or more signals into one or more cryptographic signals in a message transmitted to a receiving device, comprising:
an input of the cryptographic apparatus to receive the one or more signals;
an n-state Lab-transformed switching circuit with n>2 containing an n-state switching circuit with a first n-state reversible inverter at a first and at a second input and with at an output a second n-state inverter, wherein the first and second n-state reversible inverters in combination establish identity wherein an n-state signal is modified by the first n-state inverter into a modified n-state signal and the second n-state inverter has a structure that modifies the modified n-state signal into the n-state-signal and wherein the first n-state inverter is one of n! (factorial n) n-state inverters, the n-state Lab-transformed switching circuit being characterized by a modification of an n-state switching table that characterizes the n-state switching circuit and the n-state Lab-transformed switching circuit is enabled to process signals related to the one or more signals; and
an output of the cryptographic apparatus to provide on a communication channel to the receiving device the one or more cryptographic signals that are based on one or more signals processed by the n-state Lab-transformed switching circuit, wherein cryptographic signals generated from a first set of n-state input signals by the cryptographic apparatus with the n-state switching circuit without applying the first and second inverters are different from cryptographic signals generated from the first set of n-state input signals by the cryptographic apparatus applying the n-state Lab-transformed switching circuit; and
wherein the n-state switching circuit is characterized by one of: an addition over a finite field GF(n), a multiplication over a finite field GF(n), and a multiplication modulo-n and the n-state Lab-transformed switching circuit is part of the cryptographic apparatus to perform one of: an Advanced Encryption Standard encryption or decryption, a Rivest-Shamir-Adleman (RSA) based encryption or decryption, a Diffie-Hellman based key generation, an Elliptic Curve Cryptography (ECC) operation, a message digest generation as defined in a Federal Information Processing Standards Secure Hash Standard (SHS).

### Claim 2 (depends on 1)

The cryptographic apparatus of claim 1, wherein the n-state switching device is characterized by a modulo-n multiplication.

### Claim 3 (depends on 1)

The cryptographic apparatus of claim 1, wherein the n-state switching device is characterized by a multiplication over a finite field GF(n).

### Claim 4 (depends on 1)

The cryptographic apparatus of claim 1, wherein the n-state switching device is characterized by an addition over a finite field GF(n).

### Claim 5 (depends on 1)

The cryptographic apparatus of claim 1, wherein the n-state switching device is characterized by a modulo-n addition.

### Claim 6 (depends on 1)

The cryptographic apparatus of claim 1, wherein the n-state switching device is characterized by a two input operation characterized by an expression mod((i1+i2−1),n)+(((i1+i2−1)>=n)*1), wherein mod means modulo, i1 indicates a state of a first input and i2 indicates a state of a second input.

### Claim 7 (depends on 1)

The cryptographic apparatus of claim 1, wherein the n-state switching device is characterized by a two input operation characterized by an expression (e-i1-i2)mod-n, wherein mod means modulo, i1 indicates a state of a first input and i2 indicates a state of a second input and e is an offset.

### Claim 8 (depends on 1)

The cryptographic apparatus of claim 1, wherein the cryptographic apparatus performs a symmetric encryption or a symmetric decryption operation.

### Claim 9 (depends on 8)

The cryptographic apparatus of claim 8, wherein the cryptographic apparatus performs substantially a Lab-transformed Advanced Encryption Standard (AES) operation.

### Claim 10 (depends on 1)

The cryptographic apparatus of claim 1, wherein the cryptographic apparatus performs a public-key cryptography operation.

### Claim 11 (depends on 1)

The cryptographic apparatus of claim 1, wherein the cryptographic apparatus performs a hashing or message digest operation.

### Claim 12 (depends on 1)

The cryptographic apparatus of claim 1, wherein the cryptographic apparatus performs an elliptic curve cryptography operation.

### Claim 13 (depends on 1)

The cryptographic apparatus of claim 1, wherein the cryptographic apparatus performs an authentication operation.

### Claim 14 (depends on 1)

The cryptographic apparatus of claim 1, wherein the n-state switching device is characterized by an addition or a multiplication over a Finite Field GF(n=pk) with p a prime number greater than 1 and k an integer greater than 1 and the n-state Lab-transformed circuit is characterized by an n-state switching table that has a zero-element that is different from the n-state switching table that characterizes the n-state switching circuit.

### Claim 15 (depends on 1)

The cryptographic apparatus of claim 1, wherein the n-state switching device is characterized by a multiplication over a Finite Field GF(n=pk) with p a prime number greater than 1 and k an integer greater than 1 and the n-state Lab-transformed circuit is characterized by an n-state switching table that has a different one-element than the n-state switching table that characterizes the n-state switching circuit.

### Claim 16 (depends on 1)

The cryptographic apparatus of claim 1, wherein the cryptographic apparatus is part of the group consisting of a desktop computer, a server computer, a blade computer, a processor, a controller, a laptop computer, a tablet computer, a smartphone, a chip card, a smart card, an RFID, a FPGA, a phone, an opening device, a FOB, a TV set, and a media player.

### Claim 17

A method for cryptographic communications of one or more cryptographic signals based on one or more signals between a first computer device and a second computer device over a communication channel, comprising:
receiving on an input of the first computer device the one or more signals;
generating signals based on the one or more signals by an n-state Lab-transformed switching circuit with n>2, the n-state Lab-transformed switching circuit containing an n-state switching circuit with a first n-state reversible inverter at a first and a second input and with at an output a second n-state inverter that in combination with the first n-state reversible inverter establish identity wherein an n-state signal is modified by the first n-state inverter into a modified n-state signal and the second n-state inverter has a structure that modifies the modified n-state signal into the n-state-signal and wherein the first n-state inverter is one of n! (factorial n) n-state inverters, the n-state Lab-transformed switching circuit being characterized by a modification of an n-state switching table that characterizes the n-state switching function; and
providing by the first computer device to the second computing device over the communication channel the one or more cryptographic signals that are based on the signals generated by the n-state Lab-transformed circuit, wherein cryptographic signals generated from a first set of signals by the first computer with the n-state switching device without the first and second inverters are different from cryptographic signals generated from the first set of signals by the first computer with the n-state Lab-transformed circuit; and
wherein the n-state switching circuit is characterized by one of: an addition over a finite field GF(n), a multiplication over a finite field GF(n), and a multiplication modulo-n and the n-state Lab-transformed switching circuit is part of the cryptographic apparatus to perform one of: an Advanced Encryption Standard encryption or decryption, a Rivest-Shamir-Adleman (RSA) based encryption or decryption, a Diffie-Hellman based key generation, an Elliptic Curve Cryptography (ECC) operation, a message digest generation as defined in a Federal Information Processing Standards Secure Hash Standard (SHS).

### Claim 18 (depends on 17)

The method of claim 17, wherein the n-state Lab-transformed circuit is characterized by an operation selected from the group consisting of: an n-state zero Lab-transformed switching device, an n-state one Lab-transformed switching device, an n-state zero-one Lab-transformed switching device and an n-state k-row Lab-transformed switching device.

### Claim 19 (depends on 17)

The method of claim 17, wherein the n-state switching circuit is characterized by an n-state operation from the group of n-state operations consisting of: a modulo-n multiplication, a modulo-n addition, an addition over a finite field GF(n), an addition over a finite field GF(n=2p and p>1), a multiplication over a finite field GF(n), a multiplication over a finite field GF(n=2p and p>1), an operation defined by an expression mod((i1+i2−1),n)+(((i1+i2−1)>=n)*1), wherein mod means modulo, i1 indicates a state of a first input and i2 indicates a state of a second input; an operation defined by an expression (e-i1-i2)mod-n, wherein mod means modulo, i1 indicates a state of a first input and i2 indicates a state of a second input and e is an offset, and an operation characterized by k bitwise XOR operations.

### Claim 20 (depends on 17)

The method of claim 17, wherein the method is part of a cryptographic operation selected from the group consisting of: an encryption, a decryption, a hashing or message digest operation, a public-key cryptographic operation, an elliptic curve cryptography operation, an authentication operation and a digital signature operation.