On-chip frequency monitoring

A frequency monitor, comprising:

• a count control device configured to output a count enable signal;
• a synchronizer configured to synchronize the count enable signal with a monitored clock signal to generate a synchronized count enable signal;
• a counter configured to receive the synchronized count enable signal and the monitored clock signal, to count a number of periods of the monitored clock signal in response to the synchronized count enable signal, and to output a count value corresponding to the number of periods of the monitored clock signal;
• and
• a comparator configured to receive the count value from the counter, to receive an expected count value, to compare the count value from the counter with the expected count value, and to output a pass status signal or a fail status signal based on the comparison.

A method for frequency monitoring, comprising:

• receiving a monitored clock signal;
• counting a number of periods of the monitored clock signal over a predetermined time duration;
• generating a count value corresponding to the number of periods of the monitored clock signal counted over the predetermined time duration;
• masking out N least significant bits (LSBs) of the generated count value;
• masking out N LSBs of the expected count value;
• comparing unmasked bits of the generated count value with unmasked bits of the expected count value;
• and
• generating a pass status signal or a fail status signal based on the comparison.

A frequency monitoring system, comprising:

• a multiplexer having multiple inputs and an output, wherein each of the multiple inputs is coupled to a respective one of multiple clock signals;
• a select controller configured to instruct the multiplexer to sequentially couple each clock signal in a subset of the multiple clock signals to the output of the multiplexer;
• a frequency monitor coupled to the output of the multiplexer, wherein the frequency monitor is configured to sequentially receive each clock signal in the subset of the multiple clock signals, and wherein, for each clock signal in the subset of the multiple clock signals, the frequency monitor is configured to determine whether the clock signal is within a respective frequency range, and to output a status signal based on the determination;
• and
• a register that stores a set of monitor indicators, wherein each of the monitor indicators corresponds to a respective one of the multiple clock signals, and a value of each of the monitor indicators indicates whether the respective one of the multiple clock signals is in the subset of the multiple clock signals.