Method and apparatus for interrupting memory bank refresh
AssigneeApple Inc.
InventorsRakesh L. Notani, Kai Lun Hsiung, Peter Fu
Life of this patent
Estimating the term…
Abstract
A memory controller includes a state machine that initiates a memory refresh of a DRAM (having a number of banks) by sending thereto a refresh command. Responsive to receiving the command, the DRAM may perform a per-bank refresh in which individual ones of the banks are refreshed in succession, one at a time. Upon receiving a high priority transaction, a determination is made as to the number of memory banks that have currently been refreshed in the per-bank refresh. If the number of banks refreshed is less than a threshold value, the per-bank refresh is aborted.
Claims20
An integrated circuit comprising:
- a memory controller having an interface suitable for coupling to a dynamic random access memory (DRAM) having a plurality of banks, wherein the memory controller includes a state machine configured to:
- send a refresh command to the DRAM to initiate a per-bank refresh, the per-bank refresh comprising successively refreshing single ones of the plurality of banks;
- responsive to receiving an indication of a high-priority transaction during performing of the per-bank refresh, determining if a number of banks refreshed is at least a threshold value;
- and
- responsive to determining that the number of banks refreshed is less than the threshold value, aborting the per-bank refresh.
A method comprising:
- in a memory subsystem, a memory controller initiating a memory refresh of a dynamic random access memory (DRAM), wherein the DRAM includes a plurality of memory banks;
- performing a per-bank refresh of the DRAM, wherein the per-bank refresh comprises successively refreshing single ones of the plurality of banks;
- receiving, at the memory controller, a high priority transaction during the performing of the per-bank refresh;
- determining if a number of memory banks refreshed during the per-bank refresh is currently at least a threshold value;
- and
- responsive to determining that the number of memory banks refreshed during the per-bank refresh is less than the threshold value, aborting the per-bank refresh.
A system comprising:
- a dynamic random access memory (DRAM), the DRAM having a plurality of banks;
- a memory controller having an interface coupled to the DRAM, the memory controller including a state machine configured to:
- send a refresh command to the DRAM to initiate a per-bank refresh, the per-bank refresh comprising successively refreshing single ones of the plurality of banks of the DRAM;
- responsive to receiving an indication of a high-priority transaction during performing of the per-bank refresh, determining if a number of banks refreshed is at least a threshold value;
- and
- responsive to determining that the number of banks refreshed is less than the threshold value, aborting the per-bank refresh.
Dependencies are inferred from the claim text.