US 10,509,628 B1 · Scalable-entry FIFO memory device

Abstract

A FIFO memory device has a first number of data storage units and a second number of internal FIFO memories. Each internal FIFO memory has a third number of internal data storage units. The first number is a product of the second and third numbers. A fourth number of data inputs receives input data units in order. Input multiplexer circuitry connects each one of the data inputs to any one of the internal FIFO memories, for storage of input data units, in order, in a first layer of the FIFO memory device including corresponding storage locations in respective ones of the internal FIFO memories. The first layer may be physical, or may be logical and maintained by pointers. Output multiplexer circuitry coupled to the internal FIFO memories connects each of the internal FIFO memories to any one of the data outputs to read out the stored data units in order.

Claims20

Dependent claims

A first-in, first-out (FIFO) memory device having a first number of data storage units, the FIFO memory device comprising:

a plurality of internal FIFO memories equal in number to a second number, each internal FIFO memory in the plurality of internal FIFO memories having a third number of internal data storage units in individual storage locations, the first number, which enumerates quantity of data storage units, being a product of the second number and the third number;
a fourth number of data inputs configured to receive input data units in an order of receipt;
and
input multiplexer circuitry for selectively connecting each one of the data inputs to any one of the internal FIFO memories, to direct respective ones of the input data units, received on the data inputs, in round-robin fashion for storage as stored data units, in the order of receipt, in a first layer of the FIFO memory device defined by corresponding ones of the individual storage locations distributed across respective different ones of the internal FIFO memories.

1 more element

A method of entering data into a first-in, first-out (FIFO) memory device having a first number of data storage units, the FIFO memory device comprising a plurality of internal FIFO memories equal in number to a second number, each FIFO memory in the plurality of internal FIFO memories having a third number of internal data storage units in individual storage locations, the first number, which enumerates quantity of the data storage units, being a product of the second number and the third number, the method comprising:

receiving data units, in an order of receipt, into ones of a fourth number of data inputs of the FIFO memory device;
and
using input multiplexer circuitry that is coupled to all of the internal FIFO memories to selectively connect each one of the data inputs to any one of the internal FIFO memories, entering the data from the data inputs in round-robin fashion as stored data units, in the order of receipt, in a first layer of the FIFO memory device defined by corresponding ones of the individual storage locations distributed across respective different ones of the internal FIFO memories.

A method of reading data from a first-in, first-out (FIFO) memory device having a first number of data storage units, the FIFO memory device comprising a plurality of internal FIFO memories equal in number to a second number, each internal FIFO memory in the plurality of internal FIFO memories having a third number of internal data storage units in individual storage locations, the first number, which enumerates quantity of data storage units, being a product of the second number and the third number, the method comprising:

using output multiplexer circuitry that is coupled to all of the internal FIFO memories to selectively connect any one of the internal FIFO memories to each data unit of a fourth number of data outputs, reading out stored data units in round-robin fashion across the internal FIFO memories as the stored data units are pushed out of the internal FIFO memories, to data outputs of the FIFO memory device, in an output order corresponding to an order in which the stored data units were received by the FIFO memory device.

Dependencies are inferred from the claim text.

Scalable-entry FIFO memory device

Life of this patent

Scalable-entry FIFO memory device

Life of this patent

Abstract

Claims20