Apparatus and methods for synchronization of radar chips

A semiconductor die for controlling synchronization of a multi-chip radar system, the semiconductor die comprising:

• a phase-locked loop (PLL) configured to generate an analog-to-digital converter (ADC) clock signal based on timing of a reference clock signal;
• ADC circuitry controlled by the ADC clock signal;
• an ADC synchronization signal generation circuit configured to generate an ADC synchronization signal based on timing of the ADC clock signal;
• and
• a first pin configured to output the ADC synchronization signal and a second pin configured to output a ramp synchronization signal to thereby coordinate synchronization of the multi-chip radar system, wherein the ADC synchronization signal and the ramp synchronization signal are in different timing domains.

A semiconductor die for controlling synchronization of a multi-chip radar system, the semiconductor die comprising:

• a phase-locked loop (PLL) configured to generate an analog-to-digital converter (ADC) clock signal based on timing of a reference clock signal;
• ADC circuitry controlled by the ADC clock signal;
• an ADC synchronization signal generation circuit configured to generate an ADC synchronization signal based on timing of the ADC clock signal;
• a time-to-digital converter (TDC) configured to provide a phase adjustment to the ADC clock signal based on measuring a time delay between the reference clock signal and the ADC clock signal;
• and
• a first pin configured to output the ADC synchronization signal to thereby coordinate synchronization of the multi-chip radar system.