Bus for providing traffic management statistics to processing pipeline

A network forwarding integrated circuit (IC) comprising:

• a plurality of configurable ingress pipelines for processing packets received from ports of the network forwarding IC, each ingress pipeline comprising (i) a parser for receiving packets sent to the network forwarding IC and storing packet header fields in packet header vectors, (ii) a set of match-action stages for matching over values stored in the packet header vectors and modifying the values stored in the packet header vectors, and (iii) a deparser for constructing packets based on the packet header vectors as modified by the set of match-action stages;
• a plurality of configurable egress pipelines for processing packets to be transmitted out of ports of the network forwarding IC;
• a traffic management circuit comprising a plurality of queues, each queue corresponding to one of the egress pipelines, the traffic management circuit for receiving a packet from an ingress pipeline and enqueuing the packet into one of the queues;
• and
• a statistics bus connecting the traffic management circuit to at least a subset of the ingress pipelines, the statistics bus for providing the ingress pipelines with state information regarding the queues,
• wherein each parser comprises a first-in-first-out (FIFO) structure for storing the state information from the statistics bus,
• wherein the traffic management circuit broadcasts the state information via the statistics bus to each of the ingress pipelines and receives notifications each time a piece of state information from one of the FIFO structures is sent to a corresponding set of match-action stages.