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US 10,505,638 B2Granted
High-speed receiver architecture
AssigneeInphi Corporation
InventorsOscar Ernesto Agazzi, Diego Ernesto Crivelli, Hugo Santiago Carrer, Mario Rafael Hueda, German Cesar Augusto Luna, Carl Grace
Life of this patent
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Abstract
A receiver (e.g., for a 10G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decorder, for example, a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.
Claims56
A receiver comprising:
- an interleaved analog-to-digital converter (ADC) having more than one channel that generates signal samples from a received signal having combined non-Gaussian noise and Gaussian noise;
- a multi-channel equalizer coupled to receive the signal samples from the interleaved ADC, and to apply equalization to generate equalized samples;
- a decoder coupled to an output of the multi-channel equalizer, the decoder determining detected symbols from the equalized samples and a channel model by minimizing a cumulative metric that compensates the combined Gaussian and non-Gaussian noise in the received signal;
- and
- a channel estimator to receive the output of the multi-channel equalizer and an output of the decoder and to generate the channel model and an error feedback signal to adaptively update coefficients of the multi-channel equalizer based on the error feedback signal;
- wherein each channel of the interleaved ADC includes two pipeline units, wherein a first pipeline unit is configured for analog-to-digital conversion while the second pipeline unit is being calibrated.
3 more elements
A receiver comprising:
- an interleaved analog-to-digital converter (ADC) having more than one channel that generates signal samples from a received signal having combined non-Gaussian noise and Gaussian noise;
- wherein the interleaved ADC comprises a pipelined ADC including an input track-and-hold stage followed by a plurality of low resolution ADC stages, each ADC stage including
- a 1-bit comparator electrically coupled to an input of the ADC stage,
- a 1-bit digital-to-analog converter (DAC) electrically coupled to the 1-bit comparator,
- an analog subtractor electrically coupled to the 1-bit DAC and the input of the ADC stage,
- a residue amplifier electrically coupled to the analog subtractor, and
- a track-and-hold circuit electrically coupled to the residue amplifier;
- a multi-channel equalizer coupled to receive the signal samples from the interleaved ADC, and to apply equalization to generate equalized samples;
- a decoder coupled to an output of the multi-channel equalizer, the decoder determining detected symbols from the equalized samples and a channel model by minimizing a cumulative metric that compensates the combined Gaussian and non-Gaussian noise in the received signal;
- and
- a channel estimator to receive the output of the multi-channel equalizer and an output of the decoder and to generate the channel model and an error feedback signal to adaptively update coefficients of the multi-channel equalizer based on the error feedback signal;
- wherein the interleaved ADC further includes a lookahead pipeline configuration in which one or more of the plurality of ADC stages includes a pair of comparators configured to enable parallel interstage amplification and comparator operations.
9 more elements
A receiver comprising:
- an interleaved analog-to-digital converter (ADC) having more than one channel that generates signal samples from a received signal having combined non-Gaussian noise and Gaussian noise;
- wherein the interleaved ADC comprises a pipelined ADC including an input track-and-hold stage followed by a plurality of low resolution ADC stages, each ADC stage including
- a 1-bit comparator electrically coupled to an input of the ADC stage,
- a 1-bit digital-to-analog converter (DAC) electrically coupled to the 1-bit comparator,
- an analog subtractor electrically coupled to the 1-bit DAC and the input of the ADC stage,
- a residue amplifier electrically coupled to the analog subtractor, and
- a track-and-hold circuit electrically coupled to the residue amplifier;
- a multi-channel equalizer coupled to receive the signal samples from the interleaved ADC, and to apply equalization to generate equalized samples;
- a decoder coupled to an output of the multi-channel equalizer, the decoder determining detected symbols from the equalized samples and a channel model by minimizing a cumulative metric that compensates the combined Gaussian and non-Gaussian noise in the received signal;
- and
- a channel estimator to receive the output of the multi-channel equalizer and an output of the decoder and to generate the channel model and an error feedback signal to adaptively update coefficients of the multi-channel equalizer based on the error feedback signal;
- wherein the interleaved ADC is configured in a sub-radix architecture having more ADC stages than there are bits in the received signal.
9 more elements
A receiver comprising:
- an interleaved analog-to-digital converter (ADC) having more than one channel that generates signal samples from a received signal having combined non-Gaussian noise and Gaussian noise;
- wherein the interleaved ADC comprises a pipelined ADC including an input track-and-hold stage followed by a plurality of low resolution ADC stages, each ADC stage including
- a 1-bit comparator electrically coupled to an input of the ADC stage,
- a 1-bit digital-to-analog converter (DAC) electrically coupled to the 1-bit comparator,
- an analog subtractor electrically coupled to the 1-bit DAC and the input of the ADC stage,
- a residue amplifier electrically coupled to the analog subtractor, and
- a track-and-hold circuit electrically coupled to the residue amplifier;
- a multi-channel equalizer coupled to receive the signal samples from the interleaved ADC, and to apply equalization to generate equalized samples;
- a decoder coupled to an output of the multi-channel equalizer, the decoder determining detected symbols from the equalized samples and a channel model by minimizing a cumulative metric that compensates the combined Gaussian and non-Gaussian noise in the received signal;
- and
- a channel estimator to receive the output of the multi-channel equalizer and an output of the decoder and to generate the channel model and an error feedback signal to adaptively update coefficients of the multi-channel equalizer based on the error feedback signal;
- wherein the residue amplifiers of the ADC stages include open-loop amplifiers configured to be calibrated based on a look-up table (LUT).
9 more elements
A method for equalizing a received signal, the method comprising:
- generating, by an interleaved analog-to-digital converter (ADC) having more than one channel, signal samples from the received signal having combined non-Gaussian noise and Gaussian noise;
- applying, by a multi-channel equalizer, an equalization to the signal samples from the interleaved ADC to generate equalized samples;
- determining, by a decoder coupled to an output of the multi-channel equalizer, detected symbols from the equalized samples and a channel model by minimizing a cumulative metric that compensates the combined Gaussian and non-Gaussian noise in the received signal;
- and
- generating, by a channel estimator, the channel model and an error feedback signal to adaptively update coefficients of the multi-channel equalizer based on the error feedback signal;
- wherein each channel of the interleaved ADC includes two pipeline units, wherein a first pipeline unit is configured for analog-to-digital conversion while the second pipeline unit is being calibrated.
3 more elements
A transceiver chip for communication over an optical fiber, the transceiver chip comprising:
- a host interface for providing encoded data in a host format for transmitting over the optical fiber and for receiving decoded data in the host format originating from the optical fiber;
- transmit path circuitry to receive the encoded data from the host interface and generate an electrical signal suitable for driving a laser coupled to the optical fiber;
- an input port for receiving a received signal originating from the optical fiber having combined non-Gaussian noise and Gaussian noise;
- and
- receive path circuitry coupled between the input port and the host interface, the receive path circuitry comprising:
- an interleaved analog-to-digital converter (ADC) that generates signal samples from the received signal having the combined non-Gaussian noise and Gaussian noise;
- a multi-channel equalizer coupled to receive the signal samples from the interleaved ADC, and to apply equalization to generate equalized samples;
- a decoder coupled to an output of the multi-channel equalizer, the decoder determining detected symbols from the equalized samples and a channel model by minimizing a cumulative metric that compensates the combined Gaussian and non-Gaussian noise in the received signal, the decoder to generate the decoded data;
- and
- a channel estimator to receive the output of the multi-channel equalizer and an output of the decoder and to generate the channel model and an error feedback signal to adaptively update coefficients of the multi-channel equalizer based on the error feedback signal;
- wherein each channel of the interleaved ADC includes two pipeline units, wherein a first pipeline unit is configured for analog-to-digital conversion while the second pipeline unit is being calibrated.
8 more elements
A transceiver chip for communication over an optical fiber, the transceiver chip comprising:
- a host interface for providing encoded data in a host format for transmitting over the optical fiber and for receiving decoded data in the host format originating from the optical fiber;
- transmit path circuitry to receive the encoded data from the host interface and generate an electrical signal suitable for driving a laser coupled to the optical fiber;
- an input port for receiving a received signal originating from the optical fiber having combined non-Gaussian noise and Gaussian noise;
- and
- receive path circuitry coupled between the input port and the host interface, the receive path circuitry comprising:
- an interleaved analog-to-digital converter (ADC) that generates signal samples from the received signal having the combined non-Gaussian noise and Gaussian noise;
- a multi-channel equalizer coupled to receive the signal samples from the interleaved ADC, and to apply equalization to generate equalized samples;
- a decoder coupled to an output of the multi-channel equalizer, the decoder determining detected symbols from the equalized samples and a channel model by minimizing a cumulative metric that compensates the combined Gaussian and non-Gaussian noise in the received signal, the decoder to generate the decoded data;
- a channel estimator to receive the output of the multi-channel equalizer and an output of the decoder and to generate the channel model and an error feedback signal to adaptively update coefficients of the multi-channel equalizer based on the error feedback signal;
- and
- a timing recovery circuit coupled to the interleaved ADC and the multi-channel equalizer;
- wherein the timing recovery circuit includes a pulse preprocessor configured to adapt to time-varying impulse responses of the channels of the interleaved ADC.
9 more elements
Dependencies are inferred from the claim text.