# US 10,504,946 B2 · Array substrate manufacturing method and array substrate

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- Number: US 10,504,946 B2
- Document ID: US10504946B2
- Status: Granted
- Kind: B2
- Application number: 16/101,534
- Filed: 2018-08-13
- Published: 2018-12-20
- Granted: 2019-12-10
- Earliest claimed: 2016-02-14
- Assignees: Wuhan China Star Optoelectronics Technology Co., Ltd.
- Applicants: Wuhan China Star Optoelectronics Technology Co., Ltd.
- Inventors: Si Deng
- Web page: https://patentgrep.com/patent/US10504946B2

## CPC

- H10D 86/0231: {using masks, e.g. half-tone masks}
- G02F 1/133345: {Insulating layers (G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence)}
- G02F 1/134309: {characterised by their geometrical arrangement}
- G02F 1/13439: {characterised by their electrical, optical, physical properties; materials therefor; method of making}
- G02F 1/136209: {Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element}
- G02F 1/136227: {Through-hole connection of the pixel electrode to the active element through an insulation layer}
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- H10D 30/6715: {characterised by the doping profiles, e.g. having lightly-doped source or drain extensions}
- H10D 30/6723: {having light shields}
- H10D 30/6731: {Top-gate only TFTs}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/6745: {Polycrystalline or microcrystalline silicon}
- H10D 84/01: Manufacture or treatment
- H10D 86/01: Manufacture or treatment
- H10D 86/021: {of multiple TFTs}
- H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies}
- H10D 86/0223: {comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials}
- H10D 86/0229: {characterised by control of the annealing or irradiation parameters}
- H10D 86/0241: {using liquid deposition, e.g. printing}
- H10D 86/421: {having a particular composition, shape or crystalline structure of the active layer}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics}
- H10D 86/471: {having different architectures, e.g. having both top-gate and bottom-gate TFTs}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 89/00: Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- G02F 1/133357: {Planarisation layers}
- G02F 1/134318: {having a patterned common electrode}
- G02F 1/134372: {for fringe field switching [FFS] where the common electrode is not patterned}
- G02F 1/136231: {for reducing the number of lithographic steps}
- G02F 1/13685: {Top gates}
- G02F 2202/104: poly-Si
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS

## Abstract

An array substrate manufacturing method and an array substrate are provided. The array substrate manufacturing method uses an organic photoresist material to form a passivation protection layer for substituting the conventional passivation protection layer that is made of a silicon nitride material and applies one mask to subject the passivation protection layer and a planarization layer to exposure and development so as to obtain a third via that is located above the first drain electrode and a fourth via that is located above the second drain electrode and, thus, compared to the prior art techniques, saves one mask and reduces one etching process so as to achieve the purposes of simplifying the manufacturing process and saving manufacturing cost. The array substrate so manufactured has a simple structure and a low manufacturing cost and possesses excellent electrical performance.

## Claims

### Claim 1

An array substrate, comprising a base plate, a light shielding layer located on the base plate, a buffer layer located on the light shielding layer and the base plate, a first poly silicon section and a second poly silicon section located on the buffer layer, a first gate insulation layer and a second gate insulation layer respectively located on middle areas of the first poly silicon section and the second poly silicon section, a first gate electrode and a second gate electrode respectively located on the first gate insulation layer and the second gate insulation layer and in alignment with the first and second gate insulation layers, an interlayer insulation layer located on the first gate electrode, the second gate electrode, the first poly silicon section, the second poly silicon section, and the buffer layer, a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode located on the interlayer insulation layer, a planarization layer located on the first source electrode, the first drain electrode, the second source electrode, the second drain electrode, and the interlayer insulation layer, a common electrode located on the planarization layer, a passivation protection layer located on the common electrode and the planarization layer, and a pixel electrode located on the passivation protection layer;
the first poly silicon section comprising a first channel zone corresponding to and located under the first gate insulation layer, N type heavy doping zones respectively located at two ends, and N type light doping zones respectively located between the N type heavy doping zones and the first channel zone; the second poly silicon section comprising a first channel zone corresponding to and located under the second gate insulation layer and P type heavy doping zones respectively located at two ends;
the interlayer insulation layer comprising first vias corresponding to and located above the N type heavy doping zones and second vias corresponding to and located above the P type heavy doping zones; the first source electrode and the first drain electrode being respectively connected, through the first vias, to the N type heavy doping zones; and the second source electrode and the second drain electrode being respectively connected, through the second vias, to the P type heavy doping zones;
the planarization layer and the passivation protection layer being both made of a material comprises an organic photoresist, the passivation protection layer and the planarization layer comprising, formed therein, a third via corresponding to and located above the first drain electrode and a fourth via corresponding to and located above the second drain electrode, the pixel electrode being electrically connected, through the third via and the fourth via, to the first drain electrode and the second drain electrode respectively.

### Claim 2 (depends on 1)

The array substrate as claimed in claim 1, wherein the passivation protection layer has a dielectric constant that is around 3-4; the base plate is a transparent plate; the first metal layer, the second metal layer, and the third metal layer are formed of a material comprising one of molybdenum, titanium, aluminum, and copper or a stacked combination of multiple ones thereof; the buffer layer, the first and second gate insulation layers, and the interlayer insulation layer are each a silicon oxide layer, a silicon nitride layer, or a composite layer of stacked silicon oxide layer and silicon nitride layer; and the first transparent conductive layer and the second transparent conductive layer are formed of a material comprises a metal oxide.