# US 10,504,945 B2 · Array substrate and method for manufacturing the same, display apparatus

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- Number: US 10,504,945 B2
- Document ID: US10504945B2
- Status: Granted
- Kind: B2
- Application number: 16/086,278
- Filed: 2018-02-07
- Published: 2019-04-18
- Granted: 2019-12-10
- Earliest claimed: 2017-05-03
- Assignees: Boe Technology Group Co., Ltd.; Chongqing Boe Optoelectronics Technology Co., Ltd.
- Applicants: Boe Technology Group Co., Ltd.; Chongqing Boe Optoelectronics Technology Co., Ltd.
- Inventors: Xu Wu; Rong Wu; Chao Zhang; Zhonghao Huang
- Web page: https://patentgrep.com/patent/US10504945B2

## CPC

- H10D 86/0231: {using masks, e.g. half-tone masks}
- G02F 1/13439: {characterised by their electrical, optical, physical properties; materials therefor; method of making}
- G02F 1/1362: Active matrix addressed cells {(G02F1/134336, G02F1/134363 take precedence)}
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 86/021: {of multiple TFTs}
- H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- G02F 1/134363: {for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]}
- G02F 1/136231: {for reducing the number of lithographic steps}
- G02F 1/136236: {using a grey or half tone lithographic process}
- G02F 1/13685: {Top gates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS

## Abstract

A method for manufacturing an array substrate includes: forming a metal-oxide semiconductor layer, a first conductive layer and a second conductive layer sequentially on a substrate; and treating the metal-oxide semiconductor layer, the first conductive layer and the second conductive layer in a single patterning process using a mask, to form an active layer, pixel electrodes, a source drain pattern layer which includes source electrodes, drain electrodes and data lines, and a reserved pattern of the first conductive layer which is provided in a same layer as the pixel electrodes and formed on sides of the source electrodes and the data lines close to the active layer. The drain electrode is in direct contact with the pixel electrode, and a partial region of the pixel electrode is unobstructed from the drain electrode.

## Claims

### Claim 1

A method for manufacturing an array substrate, the method comprising:
forming a metal-oxide semiconductor layer, a first conductive layer and a second conductive layer sequentially on a substrate; and
treating the metal-oxide semiconductor layer, the first conductive layer and the second conductive layer in a single patterning process using a mask, to form an active layer, pixel electrodes, a source drain pattern layer which comprises source electrodes, drain electrodes and data lines, and a reserved pattern of the first conductive layer which is provided in a same layer as the pixel electrodes and formed on sides of the source electrodes and the data lines close to the active layer, wherein,
a drain electrode of the drain electrodes is in direct contact with a corresponding pixel electrode of the pixel electrodes, and a partial region of the pixel electrode is unobstructed from the drain electrode.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the mask comprises totally transparent portions, opaque portions, first transmittance exposure portions and second transmittance exposure portions; transmittances of the first transmittance exposure portions and the second transmittance exposure portions are different, and are less than a transmittance of the totally transparent portions;
during the patterning process for treating the metal-oxide semiconductor layer, the first conductive layer and the second conductive layer, one of the first transmittance exposure portions corresponds to a region of an active layer to be formed corresponding to a region between a source electrode and a drain electrode in the source drain pattern layer, and one of the second transmittance exposure portions corresponds to a partial region of a pixel electrode to be formed unobstructed from a corresponding drain electrode in the source drain pattern layer.

### Claim 3 (depends on 2)

The method according to claim 2, wherein treating the metal-oxide semiconductor layer, the first conductive layer and the second conductive layer in the single patterning process using the mask to form the active layer, the pixel electrodes, and the source drain pattern layer comprises:
forming a photoresist layer covering the second conductive layer;
performing a treatment comprising exposure and development for the photoresist layer via the mask, to form first photoresist reserved portions, second photoresist reserved portions, third photoresist reserved portions and photoresist complete removal regions, wherein thicknesses of each first photoresist reserved portion, each second photoresist reserved portion and each third photoresist reserved portion are successively decreased, the first photoresist reserved portions correspond to a source drain pattern layer to be formed, one of the second photoresist reserved portions corresponds to the partial region of the pixel electrode to be formed unobstructed from the corresponding drain electrode in the source drain pattern layer, one of the third photoresist reserved portions corresponds to the region of the active layer to be formed corresponding to the region between the source electrode and the drain electrode in the source drain pattern layer, and the photoresist complete removal regions correspond to remaining regions of the second conductive layer;
removing portions of the second conductive layer corresponding to the photoresist complete removal regions, and portions of the first conductive layer and portions of the metal-oxide semiconductor layer which are under the portions of the second conductive layer corresponding to the photoresist complete removal regions;
sequentially removing the third photoresist reserved portions, portions of the second conductive layer corresponding to the third photoresist reserved portions, and portions of the first conductive layer under the portions of the second conductive layer corresponding to the third photoresist reserved portions, to form an active layer, a reserved pattern of the first conductive layer that is located on the active layer, and pixel electrodes, source electrodes and data lines that are provided in a same layer as the reserved pattern of the first conductive layer;
sequentially removing the second photoresist reserved portions and portions of the second conductive layer corresponding to the second photoresist reserved portions to form drain electrodes; and
removing the first photoresist reserved portions to expose the source drain pattern layer, the pixel electrodes and regions of the active layer corresponding to regions each of which is located between the source electrode and the drain electrode.

### Claim 4 (depends on 3)

The method according to claim 3, wherein
the photoresist layer is made of a positive photoresist material,
a transmittance of the first transmittance exposure portions is larger than a transmittance of the second transmittance exposure portions; one of the totally transparent portions corresponds to a photoresist complete removal region to be formed, one of the opaque portions corresponds to a first photoresist reserved portion to be formed, one of the first transmittance exposure portions corresponds to a third photoresist reserved portion to be formed, and one of the second transmittance exposure portions corresponds to a second photoresist reserved portion to be formed.

### Claim 5 (depends on 3)

The method according to claim 3, wherein
the photoresist layer is made of a negative photoresist material,
a transmittance of the first transmittance exposure portions is less than a transmittance of the second transmittance exposure portions; one of the totally transparent portions corresponds to a first photoresist reserved portion to be formed, one of the opaque portions corresponds to a photoresist complete removal region to be formed, one of the first transmittance exposure portions corresponds to a third photoresist reserved portion to be formed, and one of the second transmittance exposure portions corresponds to a second photoresist reserved portion to be formed.

### Claim 6 (depends on 1)

The method according to claim 1, wherein the method further comprises:
forming a gate insulating layer which covers the active layer, the pixel electrodes and the source drain pattern layer; and
forming a gate metal pattern layer on the gate insulating layer; and the gate metal pattern layer comprises gate electrodes.

### Claim 7 (depends on 1)

The method according to claim 1, wherein the first conductive layer is a transparent conductive material layer.

### Claim 8 (depends on 1)

The method according to claim 1, wherein the second conductive layer is a metal layer.

### Claim 9

An array substrate, comprising a substrate, wherein the array substrate further comprises:
an active layer disposed on the substrate, wherein the active layer is made of a metal-oxide semiconductor;
a reserved pattern of a first conductive layer and pixel electrodes, wherein the reserved pattern and the pixel electrodes are disposed on the active layer; and
a source drain pattern layer disposed above the active layer,
wherein the source drain pattern layer comprises source electrodes, drain electrodes and data lines;
the source electrodes and the data lines cover the reserved pattern of the first conductive layer, and one of the drain electrodes covers a partial region of a corresponding one of the pixel electrodes.

### Claim 10 (depends on 9)

The array substrate according to claim 9, wherein the array substrate further comprises a gate insulating layer covering the active layer, the pixel electrodes, the source drain pattern layer, and a gate metal pattern layer which is disposed on the gate insulating layer, and the gate metal pattern layer comprises gate electrodes and gate lines.

### Claim 11 (depends on 9)

A display apparatus, comprising the array substrate according to claim 9.