# US 10,504,939 B2 · Integration of silicon thin-film transistors and metal-oxide thin film transistors

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- Number: US 10,504,939 B2
- Document ID: US10504939B2
- Status: Granted
- Kind: B2
- Application number: 15/899,995
- Filed: 2018-02-20
- Published: 2018-08-23
- Granted: 2019-12-10
- Earliest claimed: 2017-02-21
- Assignees: The Hong Kong University of Science and Technology
- Applicants: The Hong Kong University of Science and Technology
- Inventors: Lei Lu; Wei Zhou; Man Wong; Hoi Sing Kwok
- Web page: https://patentgrep.com/patent/US10504939B2

## CPC

- H10D 86/60: wherein the TFTs are in active matrices
- H10D 30/6731: {Top-gate only TFTs}
- H10D 30/6745: {Polycrystalline or microcrystalline silicon}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies}
- H10D 86/0231: {using masks, e.g. half-tone masks}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/471: {having different architectures, e.g. having both top-gate and bottom-gate TFTs}
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- G02F 1/13685: {Top gates}
- G02F 2202/104: poly-Si
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10K 59/1213: {the pixel elements being TFTs}
- H10P 30/22: using masks
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

This disclosure relates generally to the three-dimensional (3D) integrated thin-film transistors (TFTs) with silicon and metal-oxide (MO) semiconductors as the active layers. In one or more embodiments, an apparatus is provided that comprises a first transistor comprising a silicon active layer, and a second transistor comprising a metal oxide active layer. The second transistor is vertically stacked on the first transistor, and the first transistor and the second transistor share a gate electrode formed between the silicon active layer and the metal oxide active layer. With these embodiments, the gate electrode corresponds to a top gate of the first transistor and a bottom gate of the second transistor.

## Claims

### Claim 1

An apparatus, comprising:
a first transistor comprising a silicon active layer, wherein the silicon active layer comprises a source region, a drain region, and a channel region formed between the source region and the drain region; and
a second transistor comprising a metal oxide active layer comprising a metal oxide channel, wherein the metal oxide channel is vertically stacked on either the source region or the drain region, and wherein either the source region or the drain region serves as a bottom gate for the second transistor.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein, based on the metal oxide channel being vertically stacked on the source region, the source region is configured to operate as both an electrical source for the first transistor and the bottom gate for the second transistor.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein, based on the metal oxide channel being vertically stacked on the drain region, the drain region is configured to operate as both an electrical drain for the first transistor and the bottom gate for the second transistor.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the first transistor comprises a low-temperature polysilicon (LTPS) thin-film transistor (TFT).

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the second transistor comprises a metal oxide (MO) thin-film transistor (TFT).

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the second transistor comprises an elevated-metal metal oxide (EMMO) thin-film transistor (TFT).

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the second transistor comprises an etch-stop, metal oxide, thin-film transistor (ES-MO TFT).

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the channel region and the metal oxide channel region do not overlap.

### Claim 9

An apparatus, comprising:
a first transistor comprising a silicon active layer, wherein the silicon active layer comprises a first source region, a first drain region, and a first channel region formed between the first source region and the first drain region; and
a second transistor comprising a metal oxide active layer, a second source region and a second drain region, wherein either the second source region or the second drain region is vertically stacked on the first channel region, and wherein either the second source region or the second drain region serves as a top gate for the first transistor.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein, based on the second source region being vertically stacked on the first channel region, the second source region is configured to operate as both an electrical source for the second transistor and the top gate for the first transistor.

### Claim 11 (depends on 9)

The apparatus of claim 9, wherein, based on the second drain region being vertically stacked on the first channel region, the second drain region is configured to operate as both an electrical drain for the second transistor and the top gate for the first transistor.

### Claim 12 (depends on 9)

The apparatus of claim 9, wherein the first transistor comprises a low-temperature polysilicon (LTPS) thin-film transistor (TFT).

### Claim 13 (depends on 9)

The apparatus of claim 9, wherein the second transistor comprises a metal oxide (MO) thin-film transistor (TFT).

### Claim 14 (depends on 9)

The apparatus of claim 9, wherein the second transistor comprises an elevated-metal metal oxide (EMMO) thin-film transistor (TFT).

### Claim 15 (depends on 9)

The apparatus of claim 9, wherein the first source region and the first drain region are self-aligned relative to the second source region or the second drain region based on doping of the first source region and the first drain region using the second source region or the second drain region as a mask.

### Claim 16 (depends on 9)

The apparatus of claim 9, wherein the second transistor comprises a top-gate self-aligned (TSGA) thin-film transistor (TFT).

### Claim 17 (depends on 9)

The apparatus of claim 9, wherein the metal oxide active layer comprises the second source region, the second drain region, a second channel region formed between the second source region and the second drain region, wherein one of the second source region or the second drain region is formed between the first source region and the first drain region, and wherein the first channel region and the second channel region do not overlap.

### Claim 18

An apparatus, comprising:
a first transistor comprising a silicon active layer, wherein the silicon active layer comprises a first source region, a first drain region, and a first channel region formed between the first source region and the first drain region; and
a second transistor comprising a metal oxide active layer, wherein the metal oxide active layer comprises a second source region, a second drain region, and a second channel region formed between the second source region and the second channel region,
wherein the first transistor and the second transistor are stacked; and
wherein either the first source region or the first drain region serves as a bottom gate for the second transistor, or
wherein either the second source region or the second drain region serves as a top gate for the first transistor.

### Claim 19 (depends on 18)

The apparatus of claim 18, wherein the first transistor and the second transistor are stacked with orientations perpendicular to one another and wherein the first channel region and the second channel region do not overlap.

### Claim 20 (depends on 18)

The apparatus of claim 18, wherein the second transistor is selected from a group consisting of: a top-gate self-aligned thin-film transistor (TSGA-TFT), an elevated metal oxide thin-film transistor (EMMO-TFT), and an etch-stop, metal oxide, thin-film transistor (ES-MO TFT).