# US 10,504,938 B2 · Array substrate and method of manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,504,938 B2 - Document ID: US10504938B2 - Status: Granted - Kind: B2 - Application number: 16/106,105 - Filed: 2018-08-21 - Published: 2019-02-21 - Granted: 2019-12-10 - Earliest claimed: 2017-08-21 - Assignees: Boe Technology Group Co., Ltd.; Ordos Yuansheng Optoelectronics Co., Ltd. - Applicants: BOE Technology Group Co., Ltd.; Ordos Yuansheng Optoelectronics Co., Ltd. - Inventors: Yuelin Wang; Yanyan Zhao; Jingyi Xu; Lei Li; Yezhou Fang; Tienan Liu; Yanwei Ren; Yishan Fu; Weida Qin - Web page: https://patentgrep.com/patent/US10504938B2 ## CPC - H10D 86/60: wherein the TFTs are in active matrices - G02F 1/134309: {characterised by their geometrical arrangement} - G02F 1/136227: {Through-hole connection of the pixel electrode to the active element through an insulation layer} - H10D 30/6745: {Polycrystalline or microcrystalline silicon} - H10D 86/0212: {comprising manufacture, treatment or coating of substrates} - H10D 86/0231: {using masks, e.g. half-tone masks} - H10D 86/421: {having a particular composition, shape or crystalline structure of the active layer} - H10D 86/441: {Interconnections, e.g. scanning lines} - H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics} - G02F 1/133357: {Planarisation layers} - G02F 1/134318: {having a patterned common electrode} - G02F 1/134363: {for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]} - G02F 1/13685: {Top gates} - G02F 2201/121: common or background - G02F 2202/104: poly-Si - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS ## Abstract The present application provides an array substrate and a method of manufacturing the same. The array substrate includes a first substrate having a drain electrode protruding from a side of the first substrate; a planarization layer at the side of the first substrate where the drain electrode protrudes, the planarization layer being provided with a stepped hole on the drain electrode, and a diameter of the stepped hole decreasing along a direction from a side of the planarization layer facing away the first substrate towards a side of the planarization layer facing the first substrate; a pixel electrode at the stepped hole and connected with the drain electrode; a passivation layer covering the planarization layer and the pixel electrode; and a common electrode on the passivation layer. ## Claims ### Claim 1 An array substrate, comprising: a first substrate having a drain electrode protruding from a side of the first substrate; a planarization layer at the side of the first substrate where the drain electrode protrudes, the planarization layer being provided with a stepped hole on the drain electrode, and a diameter of the stepped hole decreasing along a direction from a side of the planarization layer facing away the first substrate towards a side of the planarization layer facing the first substrate; a pixel electrode at the stepped hole and connected with the drain electrode; a passivation layer covering the planarization layer and the pixel electrode; and a common electrode on the passivation layer, wherein an orthographic projection of the pixel electrode on the first substrate substantially completely overlaps with an orthographic projection of the stepped hole on the first substrate. ### Claim 2 (depends on 1) The array substrate of claim 1, wherein an absolute value of a difference in height between an upper surface of the planarization layer and an upper surface of the pixel electrode is smaller than a thickness of the pixel electrode, and wherein the upper surface of the planarization layer is a surface of a portion of the planarization layer at the side of the planarization layer facing away the first substrate, the portion of the planarization layer being a portion other than the stepped hole, and the upper surface of the pixel electrode is a surface of a portion of the pixel electrode at a side of the pixel electrode facing away the first substrate, the portion of the pixel electrode being on a step of the stepped hole farthest away from the first substrate. ### Claim 3 (depends on 2) The array substrate of claim 2, wherein the upper surface of the pixel electrode is flush with the upper surface of the planarization layer. ### Claim 4 (depends on 2) The array substrate of claim 2, wherein the upper surface of the pixel electrode protrudes out of the upper surface of the planarization layer by a height smaller than the thickness of the pixel electrode. ### Claim 5 (depends on 2) The array substrate of claim 2, wherein the upper surface of the pixel electrode recesses into the upper surface of the planarization layer by a depth smaller than the thickness of the pixel electrode. ### Claim 6 (depends on 1) The array substrate of claim 1, wherein a hole of the stepped hole farthest away from the first substrate has a shape and size that is in consistent with a shape and size of the pixel electrode of the array substrate. ### Claim 7 (depends on 1) The array substrate of claim 1, wherein the array substrate is a bottom-gate type array substrate or a top-gate type array substrate. ### Claim 8 (depends on 1) The array substrate of claim 1, wherein the stepped hole comprises a first portion and a second portion, the first portion being at a side of the second portion facing the first substrate, wherein the first portion has a diameter decreasing along the direction from the side of the planarization layer facing away the first substrate towards the side of the planarization layer facing the first substrate, and wherein the second portion has a constant diameter along the direction from the side of the planarization layer facing away the first substrate towards the side of the planarization layer facing the first substrate. ### Claim 9 A method of manufacturing an array substrate, comprising steps of: forming a first substrate having a drain electrode protruding from a side of the first substrate; forming a planarization layer covering the side of the first substrate where the drain electrode protrudes; providing a stepped hole at a portion of the planarization layer on the drain electrode, a diameter of the stepped hole decreasing along a direction from a side of the planarization layer facing away the first substrate towards a side of the planarization layer facing the first substrate; forming a pixel electrode, the pixel electrode being formed at the stepped hole and connected with the drain electrode; forming a passivation layer covering the planarization layer and the pixel electrode; and forming a common electrode on the passivation layer, wherein the pixel electrode and the stepped hole are formed such that an orthographic projection of the pixel electrode on the first substrate substantially completely overlaps with an orthographic projection of the stepped hole on the first substrate. ### Claim 10 (depends on 9) The method of claim 9, wherein the step of providing the stepped hole at the portion of the planarization layer on the drain electrode comprises a step of: providing the stepped hole at the portion of the planarization layer on the drain electrode by exposure and etching with a mask, wherein the mask comprises a fully transparent region and a partially transparent region surrounding and directly connected with the fully transparent region, and wherein the fully transparent region is configured to form a hole of the stepped hole closest to the first substrate, and the partially transparent region is configured to form a hole of the stepped hole other than the hole closest to the first substrate. ### Claim 11 (depends on 10) The method of claim 10, wherein an absolute value of a difference between a depth of a hole of the stepped hole farthest away from the first substrate, which is formed through the partially transparent region, and a thickness of the pixel electrode of the array substrate is smaller than the thickness of the pixel electrode. ### Claim 12 (depends on 11) The method of claim 11, wherein the depth of the hole of the stepped hole farthest away from the first substrate, which is formed through the partially transparent region, is equal to the thickness of the pixel electrode of the array substrate. ### Claim 13 (depends on 11) The method of claim 11, wherein the depth of the hole of the stepped hole farthest away from the first substrate, which is formed through the partially transparent region, is smaller than the thickness of the pixel electrode of the array substrate. ### Claim 14 (depends on 11) The method of claim 11, wherein the depth of the hole of the stepped hole farthest away from the first substrate, which is formed through the partially transparent region, is larger than the thickness of the pixel electrode of the array substrate but smaller than approximately twice of the thickness of the pixel electrode. ### Claim 15 (depends on 9) The method of claim 9, wherein the partially transparent region and the fully transparent region as an entirety have a shape and size matching with a shape and size of the pixel electrode of the array substrate, such that a hole of the stepped hole farthest away from the first substrate has a shape and size that is in consistent with the shape and size of the pixel electrode of the array substrate. ### Claim 16 (depends on 9) The method of claim 9, wherein the stepped hole is formed to comprise a first portion and a second portion, the first portion being at a side of the second portion facing the first substrate, wherein the first portion is formed to have a diameter decreasing along the direction from the side of the planarization layer facing away the first substrate towards the side of the planarization layer facing the first substrate, and wherein the second portion is formed to have a constant diameter along the direction from the side of the planarization layer facing away the first substrate towards the side of the planarization layer facing the first substrate. ### Claim 17 An array substrate, comprising: a first substrate having a drain electrode protruding from a side of the first substrate; a planarization layer at the side of the first substrate where the drain electrode protrudes, the planarization layer being provided with a stepped hole on the drain electrode, and a diameter of the stepped hole decreasing along a direction from a side of the planarization layer facing away the first substrate towards a side of the planarization layer facing the first substrate; a pixel electrode at the stepped hole and connected with the drain electrode; a passivation layer covering the planarization layer and the pixel electrode; and a common electrode on the passivation layer, wherein an absolute value of a difference in height between an upper surface of the planarization layer and an upper surface of the pixel electrode is smaller than a thickness of the pixel electrode, and wherein the upper surface of the planarization layer is a surface of a portion of the planarization layer at the side of the planarization layer facing away the first substrate, the portion of the planarization layer being a portion other than the stepped hole, and the upper surface of the pixel electrode is a surface of a portion of the pixel electrode at a side of the pixel electrode facing away the first substrate, the portion of the pixel electrode being on a step of the stepped hole farthest away from the first substrate. ### Claim 18 (depends on 17) The array substrate of claim 17, wherein the upper surface of the pixel electrode is flush with the upper surface of the planarization layer. ### Claim 19 (depends on 17) The array substrate of claim 17, wherein the upper surface of the pixel electrode protrudes out of the upper surface of the planarization layer by a height smaller than the thickness of the pixel electrode. ### Claim 20 (depends on 17) The array substrate of claim 17, wherein the upper surface of the pixel electrode recesses into the upper surface of the planarization layer by a depth smaller than the thickness of the pixel electrode.