# US 10,504,932 B2 · Display driver semiconductor device and manufacturing method thereof

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- Number: US 10,504,932 B2
- Document ID: US10504932B2
- Status: Granted
- Kind: B2
- Application number: 15/826,974
- Filed: 2017-11-30
- Published: 2018-03-22
- Granted: 2019-12-10
- Earliest claimed: 2016-07-15
- Assignees: MagnaChip Semiconductor, Ltd.
- Applicants: MagnaChip Semiconductor, Ltd.
- Inventors: Bo Seok Oh; Hee Hwan Ji; Jeong Hyeon Park
- Web page: https://patentgrep.com/patent/US10504932B2

## CPC

- H10D 86/60: wherein the TFTs are in active matrices
- G11C 19/00: Digital stores in which the information is moved stepwise, e.g. shift registers
- H03K 19/017509: {Interface arrangements}
- H10D 30/0213: {providing different silicide thicknesses on gate electrodes and on source regions or drain regions}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/608: {having non-planar bodies, e.g. having recessed gate electrodes}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10D 30/605: {having significant overlap between the lightly-doped extensions and the gate electrode}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A display driver semiconductor device includes a high voltage well region being formed on a substrate, a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device is formed on the high voltage well region and includes a first gate insulating layer. The second semiconductor device is formed adjacent to the first semiconductor device and includes a second gate insulating layer. The third semiconductor device is formed adjacent to the second semiconductor device and includes a third gate insulating layer. The first insulating layer may be formed using a chemical vapor deposition (CVD) process and the second insulating layer is formed using a thermal oxide process.

## Claims

### Claim 1

A method for manufacturing a semiconductor device, the method comprising:
forming trench isolating regions on a substrate;
forming a well region on the substrate;
forming drift regions in the well region;
forming a gate insulating layer overlapped with the drift regions;
forming a gate electrode on the gate insulating layer;
forming spacers on side walls of the gate electrode;
forming a source region and a drain region in the drift regions;
forming a first insulating layer on the substrate and the gate electrode;
forming a second insulating layer on the first insulating layer; and
forming a contact plug in the first insulating layer and the second insulating layer.

### Claim 2 (depends on 1)

The method for manufacturing the semiconductor device of claim 1, wherein the gate insulating layer comprises a first gate insulating layer and a second gate insulating layer, the first gate insulating layer being a CVD insulating layer and the second gate insulating layer being a thermal oxide layer.

### Claim 3 (depends on 1)

The method for manufacturing the semiconductor device of claim 1, wherein the source and drain regions are formed at a predetermined distance from the spacers.

### Claim 4 (depends on 1)

The method for manufacturing the semiconductor device of claim 1, further comprising:
forming a silicide blocking insulating layer on the substrate to extend to the spacers and an edge of the gate electrode.

### Claim 5 (depends on 1)

The method for manufacturing the semiconductor device of claim 1, further comprising:
forming a dummy gate electrode on the trench isolating regions.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the first insulating layer comprises a silicon nitride or a silicon oxynitride.

### Claim 7

A semiconductor device, comprising:
a thick gate insulating layer on a substrate;
a source region and a drain region formed in the substrate;
a first drift region and a second drift region surrounding the source region and the drain region, respectively;
a gate electrode on the thick gate insulation layer;
spacers formed on side walls of the gate electrode;
a silicide blocking insulating layer formed on the spacers;
a first insulating layer formed on the silicide blocking insulating layer;
a second insulating layer formed on the first insulating layer; and
a first contact plug and a second contact plug connected with the source and drain regions, respectively, in the first and second insulating layers.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the thick gate insulating layer comprises a first gate insulating layer and a second gate insulating layer, the first gate insulating layer being a chemical vapor deposition (CVD) insulating layer and the second gate insulating layer being a thermal oxide layer.

### Claim 9 (depends on 7)

The semiconductor device of claim 7, wherein the silicide blocking insulating layer is formed extended to an edge of the gate electrode.

### Claim 10 (depends on 7)

The semiconductor device of claim 7, wherein the source and drain regions are formed at a predetermined distance from the spacers.

### Claim 11 (depends on 7)

The semiconductor device of claim 7, wherein the first insulating layer comprises a silicon nitride or a silicon oxynitride.

### Claim 12

A semiconductor device, comprising:
a source region and a drain region in a substrate;
a thick gate insulating layer on the substrate;
a gate electrode on the thick gate insulation layer;
spacers formed on side walls of the gate electrode;
a silicide blocking insulating layer selectively formed on the substrate;
a thin insulating layer formed on the silicide blocking insulating layer;
an interlayer insulating layer formed on the thin insulating layer; and
a contact plug formed in the interlayer insulating layer,
wherein the silicide blocking insulating layer is formed over the side walls and a partial region of respective top surfaces of the source region, the drain region, and the gate electrode.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the source and drain regions are formed at a predetermined distance from the spacers.

### Claim 14 (depends on 12)

The semiconductor device of claim 12, further comprising a trench isolating region and a drift region formed in the substrate,
wherein the trench isolating region has a maximum depth larger than a maximum depth of the drift region which is larger than a maximum depth of the source or drain region, the respective maximum depths being measured from an upper surface of the substrate.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the source region or the drain region is disposed in the drift region.

### Claim 16 (depends on 12)

The semiconductor device of claim 12, wherein an edge portion of the gate electrode has a height greater than a height of a center portion of the gate electrode.

### Claim 17 (depends on 12)

The semiconductor device of claim 12, further comprising a silicide layer formed on the gate electrode,
wherein the silicide layer has a length smaller than a length of the gate electrode.