# US 10,504,927 B2 · Thin film transistor array panel

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- Number: US 10,504,927 B2
- Document ID: US10504927B2
- Status: Granted
- Kind: B2
- Application number: 16/069,171
- Filed: 2016-12-10
- Published: 2019-01-24
- Granted: 2019-12-10
- Earliest claimed: 2016-01-14
- Assignees: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.; Hon Hai Precision Industry Co., Ltd.
- Applicants: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.; Hon Hai Precision Industry Co., Ltd.
- Inventors: Yi-Chun Kao; Hsin-Hua Lin; Po-Li Shih; Wei-Chih Chang; I-Min Lu; I-Wei Wu
- Web page: https://patentgrep.com/patent/US10504927B2

## CPC

- H10D 86/60: wherein the TFTs are in active matrices
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 64/011: {of electrodes ohmically coupled to a semiconductor}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 86/01: Manufacture or treatment
- H10D 86/021: {of multiple TFTs}
- H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics}
- H10P 14/40: of conductive or resistive materials
- G02F 1/13306: {Circuit arrangements or driving methods for the control of single liquid crystal cells (G02F1/132, G02F1/133382 take precedence)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device comprises a multi-layered structure disposed over a substrate (101) and defining a composite lateral etch profile. The multi-layered structure includes a lower sub-layer (105-1) disposed over the substrate (101) and comprising a metal oxide material that includes indium and zinc, the indium and zinc content in the lower sub-layer (105-1) substantially defining a first indium to zinc content ratio; a middle sub-layer (105-2) disposed over the lower sub-layer (105-1) and comprising a metal material; an upper sub-layer (105-3) disposed over the middle sub-layer (105-2) and comprising a metal oxide material that includes indium and zinc, the indium to zinc content in the upper sub-layer (105-3) substantially defining a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and a lateral byproduct layer formed over the lateral etched surface, comprising substantially an metal oxide of the metal material in the middle sub-layer (105-2).

## Claims

### Claim 1

A thin film transistor array panel, comprising:
a substrate;
a first conductive layer on the substrate and comprising a gate electrode;
a channel layer on the gate electrode and insulated there-from; and
a second conductive layer on the channel layer, the second conductive layer comprising a multi-layered portion defining a source electrode and a drain electrode, wherein the multi-layered portion of the second conductive layer comprises:
a first sub-layer on the channel layer and in electrical contact with the channel layer,
a second sub-layer on the first sub-layer, the second sub-layer comprising metal, and
a third sub-layer on the second sub-layer,
wherein a gap is in the second conductive layer and between the source electrode and the drain electrode; the gap extends through the first sub-layer, the second sub-layer, and the third sub-layer;
wherein a lateral byproduct layer is formed on both a side surface of the source electrode adjacent to the gap and a side surface of the drain electrode adjacent to the gap; the lateral byproduct layer comprises an metal oxide of the metal in the second sub-layer.

### Claim 2 (depends on 1)

The thin film transistor array panel of claim 1, wherein the lateral byproduct layer is substantially free from reaching a lower layer boundary defined by the first sub-layer.

### Claim 3 (depends on 1)

The thin film transistor array panel of claim 1, wherein a gap width in the third sub-layer is wider than a gap width in the first sub-layer.

### Claim 4 (depends on 1)

The thin film transistor array panel of claim 1, wherein each of the first sub-layer and the third sub-layer comprises a metal oxide material containing indium and zinc; wherein an indium-to-zinc content ratio in the first sub-layer is greater than an indium-to-zinc content ratio in the third sub-layer.

### Claim 5 (depends on 4)

The thin film transistor array panel of claim 4, wherein the indium-to-zinc content ratio difference between the first sub-layer and the third sub-layer is not less than 20%.

### Claim 6 (depends on 5)

The thin film transistor array panel of claim 5, wherein the indium-to-zinc content ratio differentiation between the first sub-layer and the third sub-layer affects a generation of a substantially smooth and tapered lateral profile for the gap defined between the source electrode and the drain electrode.

### Claim 7 (depends on 6)

The thin film transistor array panel of claim 6, wherein the lateral profile associated with the gap defined between the source electrode and the drain electrode corresponds to a taper angle of about 40 degrees to 85 degrees with respect to a surface defined by the substrate.

### Claim 8 (depends on 5)

The thin film transistor array panel of claim 5, wherein the indium-to-zinc content ratio in the first sub-layer is in a range from about 25% to about 80%.

### Claim 9 (depends on 8)

The thin film transistor array panel of claim 8, wherein the indium-to-zinc content ratio in the first sub-layer is in a range from about 45% to about 70%.

### Claim 10 (depends on 5)

The thin film transistor array panel of claim 5, wherein the indium-to-zinc content ratio in the third sub-layer is in a range from about 5% to about 40%.

### Claim 11 (depends on 10)

The thin film transistor array panel of claim 10, wherein the indium-to-zinc content ratio in the third sub-layer is a in range from about 10% to about 35%.

### Claim 12

A thin film transistor array panel, comprising:
a substrate;
a first conductive layer on the substrate and comprising a gate electrode;
a channel layer on the gate electrode and insulated there-from; and
a second conductive layer on the channel layer, the second conductive layer comprising a multi-layered portion defining a source electrode and a drain electrode, wherein the multi-layered portion of the second conductive layer comprises:
a first sub-layer on the channel layer and in electrical contact with the channel layer,
a second sub-layer on the first sub-layer, and
a third sub-layer on the second sub-layer,
wherein the second sub-layer is made of copper or copper alloy;
wherein a gap is in the second conductive layer and between the source electrode and the drain electrode; the gap extends through the first sub-layer, the second sub-layer, and the third sub-layer; and
wherein a lateral byproduct layer is formed on both a side surface of the source electrode adjacent to the gap and a side surface of the drain electrode adjacent to the gap; the lateral byproduct layer comprises copper oxide.

### Claim 13 (depends on 12)

The thin film transistor array panel of claim 12, wherein the lateral byproduct layer is substantially free from reaching a lower layer boundary defined by the first sub-layer.

### Claim 14 (depends on 12)

The thin film transistor array panel of claim 12, wherein each of the first sub-layer and the third sub-layer comprises a metal oxide material containing indium and zinc; wherein an indium-to-zinc content ratio in the first sub-layer is greater than an indium-to-zinc content ratio in the third sub-layer.

### Claim 15 (depends on 14)

The thin film transistor array panel of claim 14, wherein the indium-to-zinc content ratio difference between the first sub-layer and the third sub-layer is not less than 20%.

### Claim 16 (depends on 15)

The thin film transistor array panel of claim 15, wherein the indium-to-zinc content ratio differentiation between the first sub-layer and the third sub-layer affects a generation of a substantially smooth and tapered lateral profile for the gap defined between the source electrode and the drain electrode.

### Claim 17 (depends on 16)

The thin film transistor array panel of claim 16, wherein the lateral profile associated with the gap defined between the source electrode and the drain electrode corresponds to a taper angle of about 40 degrees to 85 degrees with respect to a surface defined by the substrate.

### Claim 18 (depends on 5)

The thin film transistor array panel of claim 5, wherein the indium-to-zinc content ratio in the first sub-layer is in a range from about 25% to about 80%; wherein the indium-to-zinc content ratio in the third sub-layer is in a range from about 5% to about 40%.