# US 10,504,919 B2 · Semiconductor device, electronic component, and electronic device

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- Number: US 10,504,919 B2
- Document ID: US10504919B2
- Status: Granted
- Kind: B2
- Application number: 15/333,401
- Filed: 2016-10-25
- Published: 2017-05-04
- Granted: 2019-12-10
- Earliest claimed: 2015-10-30
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Munehiro Kozuma; Yoshiyuki Kurokawa
- Web page: https://patentgrep.com/patent/US10504919B2

## CPC

- H10D 84/907: {CMOS gate arrays}
- H10D 1/00: Resistors, capacitors or inductors
- H10D 30/6704: {having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 62/80: characterised by the materials
- H10D 62/875: {being semiconductor metal oxide, e.g. InGaZnO (Group II-VI materials H10D62/86; Group I-VI materials H10D62/871; Pb compounds or alloys H10D62/874)}
- H10D 86/215: {comprising FinFETs}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics}
- H10D 84/938: {Implementation of memory functions}
- H10D 84/975: {Wiring regions or routing}
- H10D 84/979: {Data lines, e.g. buses}
- H10D 84/991: {Latch-up prevention}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 46/607: {Located on parts of packages, e.g. on encapsulations or on package substrates}
- H10W 72/073: {of die-attach connectors}
- H10W 72/075: {of bond wires}
- H10W 72/354: {comprising polymers}
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/552: {comprising metals or metalloids, e.g. silver}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

To achieve high processing capability, a semiconductor device includes first and second circuits, first to third wirings, and first to fourth transistors. The first circuit is electrically connected to the first wiring and a gate of the first transistor. One of a source and a drain of the first transistor is electrically connected to the second wiring. The other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor. The second circuit is electrically connected to the first wiring and a gate of the third transistor. One of a source and a drain of the third transistor is electrically connected to the third wiring. The other of the source and the drain of the third transistor is electrically connected to a gate of the fourth transistor. One of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the second transistor. The other of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the second transistor.

## Claims

### Claim 1

A semiconductor device comprising:
a first circuit and a second circuit;
a first wiring, a second wiring, and a third wiring; and
a first transistor, a second transistor, a third transistor, and a fourth transistor,
wherein:
the first circuit is electrically connected to the first wiring,
the first circuit is electrically connected to a gate of the first transistor,
one of a source and a drain of the first transistor is electrically connected to the second wiring,
the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor,
the second circuit is electrically connected to the first wiring,
the second circuit is electrically connected to a gate of the third transistor,
one of a source and a drain of the third transistor is electrically connected to the third wiring,
the other of the source and the drain of the third transistor is electrically connected to a gate of the fourth transistor,
one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the second transistor, and
the other of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the second transistor.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the first transistor and the third transistor each comprise an active layer containing an oxide semiconductor.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1,
wherein:
the first circuit comprises a fifth transistor and a first capacitor,
the second circuit comprises a sixth transistor and a second capacitor,
the fifth transistor and the sixth transistor each comprise an active layer containing an oxide semiconductor,
one of a source and a drain of the fifth transistor is electrically connected to the first wiring,
the other of the source and the drain of the fifth transistor is electrically connected to the gate of the first transistor,
the gate of the first transistor is electrically connected to one terminal of the first capacitor,
one of a source and a drain of the sixth transistor is electrically connected to the first wiring,
the other of the source and the drain of the sixth transistor is electrically connected to the gate of the third transistor, and
the gate of the third transistor is electrically connected to one terminal of the second capacitor.

### Claim 4 (depends on 3)

The semiconductor device according to claim 3, further comprising a seventh transistor and an eighth transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to the gate of the second transistor, and
wherein one of a source and a drain of the eighth transistor is electrically connected to the gate of the fourth transistor.

### Claim 5 (depends on 4)

The semiconductor device according to claim 4, wherein the seventh transistor and the eighth transistor each comprise an active layer containing an oxide semiconductor.

### Claim 6 (depends on 2)

The semiconductor device according to claim 2, wherein the oxide semiconductor comprises In, Zn, and M, where M is at least one of Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, and Hf.

### Claim 7 (depends on 1)

An electronic component comprising:
the semiconductor device according to claim 1; and
a lead electrically connected to the semiconductor device.

### Claim 8 (depends on 7)

An electronic device comprising:
the electronic component according to claim 7; and
at least one of a display device, a touch panel, a microphone, a speaker, an operation key, and a housing.