# US 10,504,910 B2 · Memory cell having closed curve structure

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- Number: US 10,504,910 B2
- Document ID: US10504910B2
- Status: Granted
- Kind: B2
- Application number: 15/352,449
- Filed: 2016-11-15
- Published: 2017-03-02
- Granted: 2019-12-10
- Earliest claimed: 2016-11-15
- Assignees: Hewlett-Packard Development Company, L.P.
- Applicants: Hewlett-Packard Development Company, L.P.
- Inventors: Reynaldo V. Villavelez; Paul I. Mikulan
- Web page: https://patentgrep.com/patent/US10504910B2

## CPC

- H10B 41/35: with a cell select transistor, e.g. NAND
- B41J 2/04541: {Specific driving circuit}
- B41J 2/04586: {controlling heads of a type not covered by groups B41J2/04575 - B41J2/04585, or of an undefined type}
- G11C 16/10: Programming or data input circuits
- H10B 41/10: characterised by the top-view layout
- H10B 41/30: characterised by the memory core region
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/68: Floating-gate IGFETs
- H10D 30/684: {programmed by hot carrier injection}
- H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode}
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10B: ELECTRONIC MEMORY DEVICES
- B41J: TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A memory cell for a printhead includes a substrate with a source and a drain. The substrate further includes a channel located between the source and the drain and surrounding the drain. The drain can include a first rounded closed curved structure. The memory cell can include a floating gate and a control gate. The floating gate can include a second rounded closed curve structure located above the channel and below the control gate. The control gate is capacitively coupled to the floating gate.

## Claims

### Claim 1

A memory cell for a printhead, the memory cell comprising:
a substrate including a drain and a source, the drain having a first rounded closed curve structure;
a channel within the substrate and located between the drain and the source, the channel surrounding the drain;
a floating gate formed in a polysilicon layer and having a second rounded closed curve structure located above the channel;
a control gate formed in a first metal layer provided over the substrate after the polysilicon layer is provided over the substrate, the control gate capacitively coupled to the floating gate and located above the floating gate; and
a capacitor plate formed in a second metal layer different from the first metal layer, the capacitor plate electrically connected to the floating gate, the control gate capacitively coupled to the capacitor plate.

### Claim 2 (depends on 1)

The memory cell of claim 1, wherein a width of the channel is substantially uniform over a length of the channel.

### Claim 3 (depends on 1)

The memory cell of claim 1, wherein the channel is elliptically shaped from a top view of the memory cell, and the floating gate is elliptically shaped from the top view of the memory cell.

### Claim 4 (depends on 1)

The memory cell of claim 1, wherein the channel is circular from a top view of the memory cell, and the floating gate is circular from the top view of the memory cell.

### Claim 5 (depends on 1)

The memory cell of claim 1, wherein the channel comprises a plurality of straight sides and at least one rounded corner from a top view of the memory cell, and the floating gate comprises a plurality of straight sides and at least one rounded corner from the top view of the memory cell.

### Claim 6 (depends on 1)

The memory cell of claim 1, wherein the drain includes an N+ doped region.

### Claim 7 (depends on 1)

The memory cell of claim 1, wherein the channel includes a P doped region.

### Claim 8 (depends on 1)

The memory cell of claim 1, further comprising a silicon nitride layer between the control gate and the floating gate.

### Claim 9 (depends on 1)

The memory cell of claim 1, wherein the first metal layer is disposed above the second metal layer.

### Claim 10 (depends on 1)

The memory cell of claim 1, wherein the channel surrounding the drain comprises the channel encircling all sides the drain.

### Claim 11 (depends on 1)

The memory cell of claim 1, wherein the channel has a rounded closed curve structure from a top view of the memory cell, the drain has the first rounded closed curve structure from the top view of the memory cell, and the floating gate has the second rounded closed curve structure from the top view of the memory cell.

### Claim 12

An EPROM array for a printhead, comprising:
a matrix of EPROM memory cells, wherein each EPROM memory cell includes:
a substrate including a drain and a source, the drain having a rounded closed curve structure;
a channel within the substrate and located between the drain and the source, the channel surrounding the drain;
a floating gate formed in a polysilicon layer and having a second rounded closed curve structure located above the channel;
a control gate formed in a first metal layer provided over the substrate after the polysilicon layer is provided over the substrate, the control gate capacitively coupled to the floating gate and located above the floating gate; and
a capacitor plate formed in a second metal layer different from the first metal layer, the capacitor plate electrically connected to the floating gate, the control gate capacitively coupled to the capacitor plate.

### Claim 13 (depends on 12)

The EPROM array of claim 12, wherein in each EPROM memory cell, the channel is elliptically shaped from a top view of the EPROM array, and the floating gate is elliptically shaped from the top view of the EPROM array.

### Claim 14 (depends on 12)

The EPROM array of claim 12, wherein in each EPROM memory cell, the channel is circular from a top view of the EPROM array, and the floating gate is circular from the top view of the EPROM array.

### Claim 15 (depends on 12)

The EPROM array of claim 12, wherein in each EPROM memory cell, the channel includes a plurality of straight sides and at least one rounded corner from a top view of the EPROM array, and the floating gate includes a plurality of straight sides and at least one rounded corner from the top view of the EPROM array.

### Claim 16 (depends on 12)

The EPROM array of claim 12, wherein in each EPROM memory cell, a width of the channel is substantially uniform throughout the channel.

### Claim 17 (depends on 12)

The EPROM array of claim 12, wherein the control gate overlaps the floating gate above the substrate.

### Claim 18 (depends on 12)

The EPROM array of claim 12, wherein the channel has a rounded closed curve structure from a top view of the EPROM array and the channel encircles all sides the drain, the drain has the first rounded closed curve structure from the top view of the EPROM array, and the floating gate has the second rounded closed curve structure from the top view of the EPROM array.