# US 10,504,909 B2 · Plate node configurations and operations for a memory array

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,504,909 B2
- Document ID: US10504909B2
- Status: Granted
- Kind: B2
- Application number: 15/969,302
- Filed: 2018-05-02
- Published: 2018-11-15
- Granted: 2019-12-10
- Earliest claimed: 2017-05-10
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Daniele Vimercati
- Web page: https://patentgrep.com/patent/US10504909B2

## CPC

- H10B 53/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 11/221: {using ferroelectric capacitors}
- G11C 11/2259: {Cell access}
- G11C 11/2273: {Reading or sensing circuits or methods}
- G11C 11/2275: {Writing or programming circuits or methods}
- G11C 11/2293: {Timing circuits or methods}
- H10B 53/30: characterised by the memory core region
- G11C 2213/71: Three dimensional array
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Methods, systems, and devices for plate node configurations and operations for a memory array are described. A single plate node of a memory array may be coupled to multiple rows or columns of memory cells (e.g., ferroelectric memory cells) in a deck of memory cells. The single plate node may perform the functions of multiple plate nodes. The number of contacts to couple the single plate node to the substrate may be less than the number of contacts to couple multiple plate nodes to the substrate. Connectors or sockets in a memory array with a single plate node may define a size that is less than a size of the connectors or sockets with multiple plate nodes. In some examples, a single plate node of the memory array may be coupled to multiple lines of a memory cells in multiple decks of memory cells.

## Claims

### Claim 1

An electronic memory apparatus, comprising:
a three-dimensional array of ferroelectric memory cells having a first deck of ferroelectric memory cells and a second deck of ferroelectric memory cells;
a plate node coupled to a first ferroelectric memory cell coupled to a first digit line and a second ferroelectric memory cell coupled to a second digit line different from the first digit line; and
a plate driver coupled to the plate node, the plate driver operable to adjust a voltage of the plate node, wherein the plate node comprises a first portion coupled to the first deck of ferroelectric memory cells and a second portion coupled to the second deck of ferroelectric memory cells, the second portion of the plate node is coupled to the first portion of the plate node through a via structure between the first deck and the second deck.

### Claim 2 (depends on 1)

The electronic memory apparatus of claim 1, wherein:
the plate node is coupled to the first deck of ferroelectric memory cells and the second deck of ferroelectric memory cells.

### Claim 3 (depends on 1)

The electronic memory apparatus of claim 1, wherein:
the plate node comprises a sheet coupled to multiple rows or multiple columns of ferroelectric memory cells of the first deck and to multiple rows or multiple columns of ferroelectric memory cells of the second deck in the three-dimensional array.

### Claim 4 (depends on 1)

The electronic memory apparatus of claim 1, wherein:
the plate driver is positioned outside a footprint of the three-dimensional array of ferroelectric memory cells.

### Claim 5 (depends on 4)

The electronic memory apparatus of claim 4, further comprising:
an access line coupled to the plate driver, the access line extending from the plate driver to at least an edge of the footprint of the three-dimensional array.

### Claim 6 (depends on 1)

The electronic memory apparatus of claim 1, further comprising:
a connector associated with two ferroelectric memory cells of the first deck and two ferroelectric memory cells of the second deck, the connector configured to couple the associated ferroelectric memory cells to one or more digit lines.

### Claim 7 (depends on 6)

The electronic memory apparatus of claim 6, wherein the connector further comprises:
a first connection coupling the first ferroelectric memory cell of the first deck to the first digit line; and
a second connection coupling the second ferroelectric memory cell of the first deck to the second digit line.

### Claim 8 (depends on 6)

The electronic memory apparatus of claim 6, wherein:
the connector is exclusive of a connection coupling the plate node to the associated ferroelectric memory cells.

### Claim 9 (depends on 6)

The electronic memory apparatus of claim 6, wherein:
the two ferroelectric memory cells of the second deck are coupled to respective digit lines independent of the connector.

### Claim 10 (depends on 1)

The electronic memory apparatus of claim 1, further comprising:
a plurality of switching components coupled to a sense component and a plurality of digit lines, each switching component coupled to a respective digit line of the plurality of digit lines, each switching component configured to selectively couple the respective digit line to the sense component based at least in part on an access operation being performed using the respective digit line.

### Claim 11 (depends on 1)

The electronic memory apparatus of claim 1, further comprising:
a plurality of shunt switching components coupled to the plate node and a plurality of digit lines, each shunt switching component coupled to a respective digit line of the plurality of digit lines, each shunt switching component configured to selectively couple the respective digit line to the plate node based at least in part on an access operation not being performed using the respective digit line.

### Claim 12 (depends on 11)

The electronic memory apparatus of claim 11, wherein:
the plurality of shunt switching components are in a portion of a substrate below the three-dimensional array.

### Claim 13

An electronic memory apparatus, comprising:
a three-dimensional array of ferroelectric memory cells having a first deck of ferroelectric memory cells and a second deck of ferroelectric memory cells;
a plate node coupled to a first ferroelectric memory cell coupled to a first digit line and a second ferroelectric memory cell coupled to a second digit line different from the first digit line;
a plate driver coupled to the plate node, the plate driver operable to adjust a voltage of the plate node; and
a plurality of shunt switching components coupled to the plate node and a plurality of digit lines, each shunt switching component coupled to a respective digit line of the plurality of digit lines, each shunt switching component configured to selectively couple the respective digit line to the plate node based at least in part on an access operation not being performed using the respective digit line, wherein the plurality of shunt switching components are in a portion of a substrate below the three-dimensional array.

### Claim 14 (depends on 13)

The electronic memory apparatus of claim 13, wherein:
the plate node is coupled to the first deck of ferroelectric memory cells and the second deck of ferroelectric memory cells.

### Claim 15 (depends on 13)

The electronic memory apparatus of claim 13, wherein:
the plate node comprises a sheet coupled to multiple rows or multiple columns of ferroelectric memory cells of the first deck and to multiple rows or multiple columns of ferroelectric memory cells of the second deck in the three-dimensional array.

### Claim 16 (depends on 13)

The electronic memory apparatus of claim 13, wherein:
the plate driver is positioned outside a footprint of the three-dimensional array of ferroelectric memory cells.

### Claim 17 (depends on 16)

The electronic memory apparatus of claim 16, further comprising:
an access line coupled to the plate driver, the access line extending from the plate driver to at least an edge of the footprint of the three-dimensional array.

### Claim 18 (depends on 13)

The electronic memory apparatus of claim 13, wherein the plate node comprises:
a first portion coupled to the first deck of ferroelectric memory cells; and
a second portion coupled to the second deck of ferroelectric memory cells.

### Claim 19 (depends on 13)

The electronic memory apparatus of claim 13, further comprising:
a connector associated with two ferroelectric memory cells of the first deck and two ferroelectric memory cells of the second deck, the connector configured to couple the associated ferroelectric memory cells to one or more digit lines.

### Claim 20 (depends on 19)

The electronic memory apparatus of claim 19, wherein the connector further comprises:
a first connection coupling the first ferroelectric memory cell of the first deck to the first digit line; and
a second connection coupling the second ferroelectric memory cell of the first deck to the second digit line.

### Claim 21 (depends on 19)

The electronic memory apparatus of claim 19, wherein:
the connector is exclusive of a connection coupling the plate node to the associated ferroelectric memory cells.

### Claim 22 (depends on 19)

The electronic memory apparatus of claim 19, wherein:
the two ferroelectric memory cells of the second deck are coupled to respective digit lines independent of the connector.

### Claim 23 (depends on 13)

The electronic memory apparatus of claim 13, further comprising:
a plurality of switching components coupled to a sense component and the plurality of digit lines, each switching component coupled to a second respective digit line of the plurality of digit lines, each switching component configured to selectively couple the second respective digit line to the sense component based at least in part on an access operation being performed using the second respective digit line.