# US 10,504,908 B2 · High reliability OTP memory by using of voltage isolation in series

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- Number: US 10,504,908 B2
- Document ID: US10504908B2
- Status: Granted
- Kind: B2
- Application number: 16/075,982
- Filed: 2016-02-18
- Published: 2019-11-07
- Granted: 2019-12-10
- Earliest claimed: 2016-02-05
- Assignees: Sichuan Kiloway Electronics Inc.
- Applicants: Sichuan Kiloway Electronics Inc.
- Inventors: Jack Z. Peng; Junhua Mao; Xuyang Liao
- Web page: https://patentgrep.com/patent/US10504908B2

## CPC

- G11C 17/12: using field-effect devices
- G11C 17/08: using semiconductor devices, e.g. bipolar elements (G11C17/06, G11C17/14 take precedence)
- G11C 17/123: {comprising cells having several storage transistors connected in series}
- G11C 17/14: in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C 17/16: using electrically-fusible links
- H10B 20/25: One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A high-reliability one-time programmable memory adopting series high voltage partition, which relates to integrated circuit technology and comprises a first MOS tube, a second MOS tube and an anti-fuse element, wherein a gate end of the first MOS tube is connected to a second connecting line (WS), a first connecting end of the first MOS tube is connected to a gate end of the second MOS tube and a voltage limiting device, and a second connecting end of the first MOS tube is connected to a third connecting line (BL); a first connecting end of the second MOS tube is connected to a fourth connecting line (BR), a second connecting end of the second MOS tube is connected to the third connecting line (BL), and a gate end of the second MOS tube is connected to the voltage limiting device and the second connecting end of the first MOS tube.

## Claims

### Claim 1

A high reliable OTP memory by using of Voltage Isolation in Series, comprising: a first MOS transistor, a second MOS transistor and a anti-fuse element, wherein
a gate of the first MOS transistor is connected to a second line WS, a first end of the first MOS transistor is connected to a gate of the second MOS transistor, and to a voltage limit device, a second end of the first MOS transistor is connected to a third line BL;
a first end of the second MOS transistor is connected to a fourth line BR, and a second end of the second MOS transistor is connected to the third line BL, the gate of the second MOS transistor is connected to the voltage limit device and to the second end of the first MOS transistor;
the high reliable OTP memory by using of Voltage Isolation in Series further comprises the voltage-limit device having one control end and two connection ends, the control end of the voltage-limit device is connected to a control line WB, a first connection end of the voltage-limit device is connected to the anti-fuse element and a first line WP across through the anti-fuse element, a second connection end of the voltage-limit device is connected to the gate of the second MOS transistor and to the first end of the first MOS transistor.

### Claim 2 (depends on 1)

The high reliable OTP memory of claim 1, wherein the voltage-limit device is a third MOS transistor.

### Claim 3 (depends on 2)

The high reliable OTP memory of claim 2, wherein the first end of the first MOS transistor is a first drain, and the second end of the first MOS transistor is a first source; the first end of the second MOS transistor is a second drain, and the second end of the second MOS transistor is a second source; a first end of the third MOS transistor is a third drain, and a second end of the third MOS transistor is a third source.

### Claim 4 (depends on 2)

The high reliable OTP memory of claim 2, wherein all of the first MOS transistor, the second MOS transistor and the third MOS transistor are N-type transistors (NMOS) or P-type transistors (PMOS).

### Claim 5 (depends on 2)

The high reliable OTP memory of claim 2, wherein all of the first MOS transistor, the second MOS transistor and the third MOS transistor are symmetrical MOS transistors.