# US 10,504,907 B2 · Antifuse array and method of forming antifuse using anodic oxidation

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- Number: US 10,504,907 B2
- Document ID: US10504907B2
- Status: Granted
- Kind: B2
- Application number: 15/939,485
- Filed: 2018-03-29
- Published: 2018-08-02
- Granted: 2019-12-10
- Earliest claimed: 2014-03-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.; National Taiwan University
- Applicants: Taiwan Semiconductor Manufacturing Company Limited; National Taiwan University
- Inventors: Jenn-Gwo Hwu; Wei-Cheng Tian; Samuel C. Pan; Chao-Hsiung Wang; Chi-Wen Liu
- Web page: https://patentgrep.com/patent/US10504907B2

## CPC

- H10W 20/491: {Antifuses, i.e. interconnections changeable from non-conductive to conductive}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- B82Y 40/00: Manufacture or treatment of nanostructures
- C25D 11/02: Anodisation
- H10B 20/25: One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/01: Manufacture or treatment
- H10D 64/514: {characterised by the insulating layers}
- H10D 64/517: {characterised by the conducting layers}
- H10P 14/6324: {Formation by anodic treatments, e.g. anodic oxidation}
- H10W 20/031: {of conductive parts of the interconnections}
- H10W 20/065: {by making at least a portion of the conductive part non-conductive, e.g. by oxidation}
- H10W 20/0554: {of nanotubes or nanowires}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- C25D: PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for forming an antifuse on a substrate is provided, which comprises: forming a first conductive material on the substrate; placing the first conductive material in an electrolytic solution; performing anodic oxidation on the first conductive material to form a nanowire made of the first conductive material and surrounded by a first dielectric material formed during the anodic oxidation and to form the antifuse on the nanowire; and forming a second conductive material on the antifuse to sandwich the antifuse between the first conductive material and the second conductive material.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a first protrusion on the substrate, wherein a height of the first protrusion at edges of the first protrusion in a first direction perpendicular to a major surface of the substrate is greater than a height of the first protrusion at a center of the first protrusion in the first direction, the first protrusion having a tapered recess;
a first select line in the first protrusion; and
a first program line on top of the tapered recess of the first protrusion, wherein the first protrusion comprises a first antifuse between the first select line and the first program line.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the substrate comprises a first ridge under the first protrusion.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first select line is made of silicon, and the first protrusion is made of silicon oxide produced by anodic oxidation.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the first select line is made of metal, and the first protrusion is made of metal oxide produced by anodic oxidation.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the first antifuse is made of a material having dielectric strength of about 10 MV/m to about 1000 MV/m.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising:
a second protrusion adjacent to the first protrusion and on the substrate; and
a second select line in the second protrusion, wherein the second protrusion comprises a second antifuse between the second select line and the first program line.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the first protrusion has a width of about 5 nm to about 100 nm.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the first protrusion has a height of about 5 nm to about 500 nm.

### Claim 9

A one-time programmable device, comprising:
a nanowire made of a first conductive material;
a gate made of a second conductive material; and
a gate oxide surrounding the nanowire, at least a portion of the gate oxide extending between the nanowire and the gate, the gate oxide being anodically oxidized from the first conductive material, wherein the gate oxide works as an antifuse between the nanowire and the gate;
wherein the gate oxide has a tapered recess, wherein a depth of the tapered recess measured in a first direction is greater at a center of the gate oxide than a depth of the tapered recess measured in the first direction at edges of the gate oxide, and wherein the gate is positioned on top of the tapered recess, the gate oxide extending between the gate and the nanowire in the first direction.

### Claim 10 (depends on 9)

The one-time programmable device of claim 9, further comprising:
a source connected to a first terminal of the nanowire; and
a drain connected to a second terminal of the nanowire.

### Claim 11 (depends on 9)

The one-time programmable device of claim 9, wherein the gate oxide is made of a material having dielectric strength of about 10 MV/m to about 1000 MV/m.

### Claim 12

A semiconductor device, comprising:
a substrate;
a first protrusion on the substrate, the first protrusion having a tapered recess, the first protrusion having a first height at edges of the first protrusion, the first height being measured in a first direction perpendicular to a major surface of the substrate, the first protrusion having a second height at a center of the first protrusion, the second height being measured in the first direction, the second height being less than the first height;
a first line in the first protrusion; and
a second line on top of the tapered recess of the first protrusion, wherein the first protrusion comprises a first antifuse between the first and second lines.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the substrate comprises a first ridge under the first protrusion.

### Claim 14 (depends on 12)

The semiconductor device of claim 12, wherein the first line is made of silicon, and the first protrusion is made of silicon oxide.

### Claim 15 (depends on 12)

The semiconductor device of claim 12, wherein the first line is made of metal, and the first protrusion is made of metal oxide.

### Claim 16 (depends on 12)

The semiconductor device of claim 12, wherein the first antifuse is made of a material having dielectric strength of about 10 MV/m to about 1000 MV/m.

### Claim 17 (depends on 12)

The semiconductor device of claim 12, further comprising:
a second protrusion adjacent to the first protrusion and on the substrate; and
a third line in the second protrusion, wherein the second protrusion comprises a second antifuse between the second and third lines.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein the substrate comprises a first ridge below the first protrusion and a second ridge below the second protrusion.

### Claim 19 (depends on 12)

The semiconductor device of claim 12, wherein the first protrusion has a width of about 5 nm to about 100 nm.

### Claim 20 (depends on 12)

The semiconductor device of claim 12, wherein the first protrusion has a height of about 5 nm to about 500 nm.