# US 10,504,906 B2 · FinFET SRAM layout and method of making the same

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- Number: US 10,504,906 B2
- Document ID: US10504906B2
- Status: Granted
- Kind: B2
- Application number: 15/830,671
- Filed: 2017-12-04
- Published: 2019-06-06
- Granted: 2019-12-10
- Earliest claimed: 2017-12-04
- Assignees: Globalfoundries Inc.
- Applicants: GLOBALFOUNDRIES Inc.
- Inventors: Ming-Cheng Chang; Nigel Chan; Ralf Van Bentum
- Web page: https://patentgrep.com/patent/US10504906B2

## CPC

- H10B 10/12: {comprising a MOSFET load element}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- H10D 89/10: Integrated device layouts
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of forming a finFET SRAM and related device, are provided. Embodiments include forming a plurality of silicon fins in a substrate; and forming a gate over each of the fins, wherein all of the fins are diagonally skewed in a single direction relative to the gates, and all of the gates extend in a single direction relative to the respective fins.

## Claims

### Claim 1

A method comprising:
forming a plurality of silicon fins in a substrate;
forming a gate over each of the fins; and
forming source/drain (S/D) contacts in a diagonally skewed direction relative to the gates; and
wherein all of the fins are diagonally skewed in a single direction relative to the gates, and
wherein all of the gates extend in a single direction relative to the respective fins.

### Claim 2 (depends on 1)

The method according to claim 1, comprising:
forming the fins and gates as a fin field effect transistor (finFET) memory device.

### Claim 3 (depends on 2)

The method according to claim 2, wherein the finFET memory device comprises static random-access memory (SRAM) cell.

### Claim 4 (depends on 3)

The method according to claim 3, wherein the SRAM cell comprises a six transistor finFET SRAM high density (HD) cell.

### Claim 5 (depends on 1)

The method according to claim 1, wherein the single direction of the fins is non-orthogonal relative to the respective gates.

### Claim 6 (depends on 1)

The method according to claim 1, wherein the single direction of the gates is non-orthogonal relative to the respective fins.

### Claim 7 (depends on 1)

The method according to claim 1, comprising:
forming each fin at an angle of 50 to 70 degrees relative to the respective gate.

### Claim 8 (depends on 7)

The method according to claim 7, comprising:
forming each fin at an angle of 66 degrees relative to the respective gate.

### Claim 9

A device comprising:
a plurality of silicon fins formed in a substrate; and
a gate formed over each of the fins,
wherein all of the fins are diagonally skewed in a single direction relative to the gates, and
wherein all of the gates extend in a single direction relative to the respective fins, and
wherein the finFET memory device comprises static random-access memory (SRAM) cell.

### Claim 10 (depends on 9)

The device according to claim 9, comprising:
the fins and gates formed as a fin field effect transistor (finFET) memory device.

### Claim 11 (depends on 9)

The device according to claim 9, wherein the SRAM cell comprises a six transistor finFET SRAM high density (HD) cell.

### Claim 12 (depends on 9)

The device according to claim 9, wherein the single direction of the fins is non-orthogonal relative to the respective gates.

### Claim 13 (depends on 9)

The device according to claim 9, wherein the single direction of the gates is non-orthogonal relative to the respective fins.

### Claim 14 (depends on 9)

The device according to claim 9, comprising:
each fin formed at an angle of 50 to 70 degrees relative to the respective gate.

### Claim 15 (depends on 14)

The device according to claim 14, comprising:
each fin formed at an angle of 66 degrees relative to the respective gate.

### Claim 16 (depends on 9)

The device according to claim 9, further comprising:
source/drain (S/D) contacts formed in a diagonally skewed direction relative to the gates.

### Claim 17

A method comprising:
forming a plurality of silicon fins in a substrate; and
forming a gate over each of the fins,
wherein all of the fins are diagonally skewed in a single direction at an angle relative to the gates,
wherein all of the gates extend in a single direction relative to the respective fins, and
the fins and gates comprise a six transistor finFET SRAM high density (HD) cell.

### Claim 18 (depends on 17)

The method according to claim 17, comprising:
forming each fin at an angle of 66 degrees relative to the respective gate.