# US 10,504,903 B1 · Semiconductor device and manufacturing method thereof

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- Number: US 10,504,903 B1
- Document ID: US10504903B1
- Status: Granted
- Kind: B1
- Application number: 16/000,911
- Filed: 2018-06-06
- Published: 2019-11-28
- Granted: 2019-12-10
- Earliest claimed: 2018-05-24
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Zhibiao Zhou
- Web page: https://patentgrep.com/patent/US10504903B1

## CPC

- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 64/311: {Gate electrodes for field-effect devices}
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B 12/03: {Making the capacitor or connections thereto}
- H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}
- H10B 53/00: Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10D 30/6729: {characterised by the electrodes}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10N 70/8836: {Complex metal oxides, e.g. perovskites, spinels}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A semiconductor device includes a substrate, a semiconductor channel layer, a gate electrode, and a first memory structure. The semiconductor channel layer is disposed on the substrate. The gate electrode and the first memory structure are disposed on the semiconductor channel layer. The first memory structure includes a first bottom plate, a first top plate, and a first memory element layer. The first top plate is disposed on the first bottom plate. The first memory element layer is disposed between the first bottom plate and the first top plate. The first bottom plate contacts the semiconductor channel layer. Purposes of process simplification and/or memory density enhancement may be achieved by integrating a transistor with a memory structure.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a semiconductor channel layer disposed on the substrate;
a gate electrode disposed on the semiconductor channel layer;
a first memory structure disposed on the semiconductor channel layer, wherein the first memory structure comprises:
a first bottom plate;
a first top plate disposed on the first bottom plate; and
a first memory element layer disposed between the first bottom plate and the first top plate, wherein the first bottom plate contacts the semiconductor channel layer;
an interconnection structure disposed between the substrate and the semiconductor channel layer; and
a metal oxide semiconductor (MOS) structure disposed between the substrate and the interconnection structure.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a gate dielectric layer disposed on the semiconductor channel layer and the first memory structure, wherein the gate electrode is disposed on the gate dielectric layer.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein a part of the first top plate is disposed between the gate electrode and the semiconductor channel layer in a thickness direction of the substrate.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the first memory structure comprises a random access memory (RAM) structure, a resistive RAM (RRAM) structure, a phase change RAM (PCRAM) structure, a magnetoresistive RAM (MRAM) structure, or a ferroelectric RAM (FeRAM) structure.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the first memory element layer comprises a material with switchable resistance, a phase change material, a magnetic tunnel junction (MTJ) film stack, or a ferroelectric material.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a source/drain electrode disposed on the semiconductor channel layer; and
a gate dielectric layer disposed on the semiconductor channel layer, the first memory structure, and the source/drain electrode, wherein the gate electrode, the gate dielectric layer, the semiconductor channel layer, the source/drain electrode, and the first bottom plate form a transistor.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a second memory structure disposed on the semiconductor channel layer, wherein the first memory structure and the second memory structure are disposed at two opposite sides of the gate electrode respectively, and the second memory structure comprises:
a second bottom plate;
a second top plate disposed on the second bottom plate; and
a second memory element layer disposed between the second bottom plate and the second top plate, wherein the second bottom plate contacts the semiconductor channel layer.

### Claim 8 (depends on 7)

The semiconductor device according to claim 7, wherein a part of the second top plate is disposed between the gate electrode and the semiconductor channel layer in a thickness direction of the substrate.

### Claim 9 (depends on 7)

The semiconductor device according to claim 7, wherein the second memory structure comprises a random access memory (RAM) structure, a resistive RAM (RRAM) structure, a phase change RAM (PCRAM) structure, a magnetoresistive RAM (MRAM) structure, or a ferroelectric RAM (FeRAM) structure.

### Claim 10 (depends on 7)

The semiconductor device according to claim 7, further comprising:
a gate dielectric layer disposed on the semiconductor channel layer, the first memory structure, and the second memory structure, wherein the gate electrode, the gate dielectric layer, the semiconductor channel layer, the first bottom plate, and the second bottom plate form a transistor.

### Claim 11

A manufacturing method of a semiconductor device, comprising:
forming a semiconductor channel layer on a substrate;
forming a gate electrode on the semiconductor channel layer; and
forming a first memory structure on the semiconductor channel layer, wherein the first memory structure comprises:
a first bottom plate;
a first top plate disposed on the first bottom plate; and
a first memory element layer disposed between the first bottom plate and the first top plate, wherein the first bottom plate contacts the semiconductor channel layer;
forming an interconnection structure, wherein the interconnection structure is located between the substrate and the semiconductor channel layer; and
forming a metal oxide semiconductor (MOS) structure, wherein the MOS structure is located between the substrate and the interconnection structure.

### Claim 12 (depends on 11)

The manufacturing method of the semiconductor device according to claim 11, further comprising:
forming a gate dielectric layer on the semiconductor channel layer and the first memory structure before the step of forming the gate electrode, wherein the gate electrode is formed on the gate dielectric layer.

### Claim 13 (depends on 11)

The manufacturing method of the semiconductor device according to claim 11, wherein a part of the first top plate is disposed between the gate electrode and the semiconductor channel layer in a thickness direction of the substrate.

### Claim 14 (depends on 11)

The manufacturing method of the semiconductor device according to claim 11, further comprising:
forming a source/drain electrode on the semiconductor channel layer, wherein the source/drain electrode and the first bottom plate are formed concurrently by the same process.

### Claim 15 (depends on 11)

The manufacturing method of the semiconductor device according to claim 11, further comprising:
forming a second memory structure on the semiconductor channel layer, wherein the first memory structure and the second memory structure are formed at two opposite sides of the gate electrode respectively, and the second memory structure comprises:
a second bottom plate;
a second top plate disposed on the second bottom plate; and
a second memory element layer disposed between the second bottom plate and the second top plate, wherein the second bottom plate contacts the semiconductor channel layer.

### Claim 16 (depends on 15)

The manufacturing method of the semiconductor device according to claim 15, wherein a part of the second top plate is disposed between the gate electrode and the semiconductor channel layer in a thickness direction of the substrate.

### Claim 17 (depends on 15)

The manufacturing method of the semiconductor device according to claim 15, further comprising:
forming a gate dielectric layer on the semiconductor channel layer, the first memory structure, and the second memory structure, wherein the gate electrode is formed on the gate dielectric layer.

### Claim 18 (depends on 15)

The manufacturing method of the semiconductor device according to claim 15, wherein the first memory structure and the second memory structure are formed concurrently by the same process.

### Claim 19 (depends on 18)

The manufacturing method of the semiconductor device according to claim 18, wherein the step of forming the first memory structure and the second memory structure comprises:
forming a first conductive layer on the semiconductor channel layer;
forming a memory element material on the first conductive layer;
forming a second conductive layer on the memory element material; and
patterning the second conductive layer, the memory element material, and the first conductive layer to form the first memory structure and the second memory structure.