# US 10,504,902 B2 · Data storage devices and methods of manufacturing the same

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- Number: US 10,504,902 B2
- Document ID: US10504902B2
- Status: Granted
- Kind: B2
- Application number: 15/959,366
- Filed: 2018-04-23
- Published: 2019-03-21
- Granted: 2019-12-10
- Earliest claimed: 2017-09-19
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Hong Hyun Kim; Seung Pil Ko; Hyunchul Shin; Kilho Lee
- Web page: https://patentgrep.com/patent/US10504902B2

## CPC

- G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell}
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10N 50/01: Manufacture or treatment
- H10N 50/10: Magnetoresistive devices
- H10N 50/80: Constructional details
- G11C 11/165: {Auxiliary circuits}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

Disclosed are data storage devices and methods of manufacturing the same. The methods may include providing a substrate including a cell region and a peripheral circuit region, forming a data storage layer on the cell region and the peripheral circuit region of the substrate, selectively forming a mask layer on a portion of the data storage layer that is formed on the peripheral circuit region, forming a top electrode layer on the data storage layer and the mask layer, patterning the top electrode layer to form a plurality of top electrodes on the cell region, and patterning the data storage layer using the plurality of top electrodes as an etch mask to form a plurality of data storage parts on the cell region. While patterning the top electrode layer, the mask layer on the peripheral circuit region may serve as an etch stop layer.

## Claims

### Claim 1

A method of manufacturing a data storage device, the method comprising:
providing a substrate including a cell region and a peripheral circuit region;
forming a data storage layer on the cell region and the peripheral circuit region of the substrate;
selectively forming a mask layer on a portion of the data storage layer that is formed on the peripheral circuit region;
forming a top electrode layer on the data storage layer and the mask layer;
patterning the top electrode layer to form a plurality of top electrodes on the cell region; and
patterning the data storage layer using the plurality of top electrodes as an etch mask to form a plurality of data storage parts on the cell region,
wherein, while patterning the top electrode layer, the mask layer on the peripheral circuit region serves as an etch stop layer.

### Claim 2 (depends on 1)

The method of claim 1, further comprising forming an interlayer dielectric layer between the substrate and the data storage layer,
wherein patterning the data storage layer comprises etching an upper portion of the interlayer dielectric layer, and
wherein a top surface of a first portion of the interlayer dielectric layer that is formed on the cell region is located at a level different from that of a top surface of a second portion of the interlayer dielectric layer that is formed on the peripheral circuit region after patterning the data storage layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein, while patterning the data storage layer, the mask layer on the peripheral circuit region protects the interlayer dielectric layer beneath the mask layer.

### Claim 4 (depends on 1)

The method of claim 1, further comprising forming a bottom electrode layer between the substrate and the data storage layer,
wherein patterning the data storage layer using the plurality of top electrodes as an etch mask comprises patterning the bottom electrode layer to form a plurality of bottom electrodes.

### Claim 5 (depends on 1)

The method of claim 1, wherein patterning the data storage layer comprises performing an ion beam etching process.

### Claim 6 (depends on 5)

The method of claim 5, wherein, when the ion beam etching process is performed, the mask layer is removed from the peripheral circuit region.

### Claim 7 (depends on 1)

The method of claim 1, wherein the data storage layer comprises:
a fixed layer having a fixed magnetization direction;
a free layer having a variable magnetization direction; and
a tunnel barrier between the fixed layer and the free layer.

### Claim 8

A method of manufacturing a data storage device, the method comprising:
providing a substrate including a first region and a second region;
forming a first interlayer dielectric layer on the first region and the second region of the substrate;
forming a data storage layer on the first interlayer dielectric layer;
selectively forming a mask layer on a portion of the data storage layer that is formed on the second region;
forming a top electrode layer on the data storage layer and the mask layer;
patterning the top electrode layer to form a plurality of top electrodes on the first region; and
patterning the data storage layer using the plurality of top electrodes as an etch mask to form a plurality of data storage parts on the first region,
wherein, during patterning the data storage layer, an upper portion of the first interlayer dielectric layer is etched such that a first portion of the first interlayer dielectric layer that is formed on the first region has a top surface at a different level from that of a top surface of a second portion of the first interlayer dielectric layer that is formed on the second region.

### Claim 9 (depends on 8)

The method of claim 8, wherein patterning the top electrode layer comprises exposing the mask layer on the second region.

### Claim 10 (depends on 8)

The method of claim 8, wherein the first interlayer dielectric layer has a sidewall connecting the top surface of the first portion of the first interlayer dielectric layer that is formed on the first region to the top surface of the second portion of the first interlayer dielectric layer that is formed on the second region, and
wherein the sidewall has an angle with respect to a top surface of the substrate of about 35 degrees to about 90 degrees.

### Claim 11 (depends on 8)

The method of claim 8, further comprising forming a bottom electrode layer between the first interlayer dielectric layer and the data storage layer,
wherein patterning the data storage layer using the plurality of top electrodes as an etch mask comprises patterning the bottom electrode layer to form a plurality of bottom electrodes.

### Claim 12 (depends on 8)

The method of claim 8, further comprising:
forming a memory transistor on the first region of the substrate;
forming a peripheral transistor on the second region of the substrate; and
forming a cell contact plug that penetrates the first interlayer dielectric layer to electrically connect with the memory transistor,
wherein the data storage layer is formed on the cell contact plug.

### Claim 13 (depends on 8)

The method of claim 8, wherein, during patterning the data storage layer, the upper portion of the first interlayer dielectric layer is etched to form a recess in the first interlayer dielectric layer between two adjacent ones of the plurality of data storage parts.

### Claim 14

A method of manufacturing a data storage device, the method comprising:
forming a data storage layer extending on a first region and a second region of a substrate;
forming a mask layer on a first portion of the data storage layer that is formed on the second region of the substrate;
forming a top electrode layer on the data storage layer and the mask layer;
forming a plurality of mask patterns on the top electrode layer on the first region of the substrate;
forming a plurality of top electrodes on the first region by etching the top electrode layer using the plurality of mask patterns as an etch mask until a second portion of the data storage layer that is formed on the first region and the mask layer that is formed on the second region are exposed; and
forming a plurality of data storage elements on the first region by etching the data storage layer using the plurality of top electrodes as an etch mask.

### Claim 15 (depends on 14)

The method of claim 14, wherein forming the mask layer on the first portion of the data storage layer that is formed on the second region of the substrate comprises:
forming a preliminary mask layer on the first region and the second region of the substrate; and
removing a portion of the preliminary mask layer that is formed on the first region of the substrate.

### Claim 16 (depends on 14)

The method of claim 14, further comprising forming a first top electrode layer extending on the first region and the second region of the substrate before forming the mask layer,
wherein the first top electrode layer extends between the data storage layer and the mask layer,
wherein forming the top electrode layer on the data storage layer and the mask layer comprises forming a second top electrode layer contacting an upper surface of the first top electrode layer formed on the first region of the substrate and contacting an upper surface of the mask layer formed on the second region of the substrate, and
wherein forming the plurality of top electrodes comprises sequentially etching the second top electrode layer and the first top electrode layer using the plurality of mask patterns as an etch mask until the second portion of the data storage layer that is formed on the first region and the mask layer that is formed on the second region are exposed.

### Claim 17 (depends on 16)

The method of claim 16, wherein a portion of the first top electrode layer is between the data storage layer and the mask layer after forming the plurality of top electrodes.

### Claim 18 (depends on 14)

The method of claim 14, further comprising:
sequentially forming an interlayer dielectric layer and a bottom electrode layer on the substrate before forming the data storage layer; and
forming a plurality of bottom electrodes on the first region by etching the bottom electrode layer using the plurality of top electrodes as an etch mask after forming the plurality of data storage elements,
wherein an upper surface of a portion of the interlayer dielectric layer that is adjacent an interface between the first region and the second region has a stepped shape.

### Claim 19 (depends on 18)

The method of claim 18, wherein a side of the stepped shape of the interlayer dielectric layer has an angle of about 35 degrees to about 90 degrees with respect to an upper surface of the substrate.

### Claim 20 (depends on 18)

The method of claim 18, wherein the portion of the interlayer dielectric layer has a first top surface on the first region of the substrate and a second top surface on the second region of the substrate, and the second top surface is higher than the first top surface.