# US 10,504,901 B2 · Substrate processing method and device manufactured using the same

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- Number: US 10,504,901 B2
- Document ID: US10504901B2
- Status: Granted
- Kind: B2
- Application number: 15/951,644
- Filed: 2018-04-12
- Published: 2018-11-01
- Granted: 2019-12-10
- Earliest claimed: 2017-04-26
- Assignees: ASM IP Holding B.V.
- Applicants: ASM IP Holding B.V.
- Inventors: Tae Hee Yoo; Yoon Ki Min; Yong Min Yoo
- Web page: https://patentgrep.com/patent/US10504901B2

## CPC

- H10W 70/095: {of vias therein}
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10W 10/012: {using local oxidation of silicon [LOCOS]}
- H10W 10/13: formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
- H10W 20/0698: {Local interconnections}
- G11C 8/14: Word line organisation; Word line lay-out
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A substrate processing method includes stacking a plurality of stack structures each including an insulating layer and a sacrificial layer, on one another. The method also includes generating a stair structure by etching the stack structures and generating a separation layer on a side surface of the stair structure. The method further includes removing the sacrificial layer and generating conductive word line structures in spaces from which the sacrificial layer is removed. The separation layer is provided between the conductive word line structures.

## Claims

### Claim 1

A substrate processing method comprising:
stacking a plurality of stack structures each comprising an insulating layer and a sacrificial layer formed over the insulating layer;
generating a stair structure by partially removing the stack structures, the stair structure comprising a plurality of side surfaces;
generating a separation layer on each of the plurality of side surfaces of the stair structure; and
replacing the sacrificial layer of each stack structure with one of a plurality of conductive word line structures,
wherein the separation layer is provided between adjacent ones of the conductive word line structures,
wherein the conductive word line structure comprises a first conductive layer extending toward a channel and a second conductive layer on the first conductive layer, and
wherein at least a part of a side surface of the first conductive layer is in contact with the separation layer.

### Claim 2

A substrate processing method comprising:
stacking a plurality of stack structures each comprising an insulating layer and a sacrificial layer formed over the insulating layer;
generating a stair structure by partially removing the stack structures, the stair structure comprising a plurality of side surfaces;
generating a separation layer on each of the plurality of side surfaces of the stair structure;
replacing the sacrificial layer of each stack structure with one of a plurality of conductive word line structures, wherein the separation layer is provided between adjacent ones of the conductive word line structures;
generating a pad layer on the sacrificial layer; and
generating an interlayer insulating layer on the stair structure,
wherein replacing the sacrificial layer comprises:
removing the sacrificial layer and the pad layer; and
filling a conductive material in a space from which the sacrificial layer and the pad layer are removed.

### Claim 3 (depends on 2)

The substrate processing method of claim 2, wherein a short circuit between the adjacent ones of the conductive word line structures is prevented by the separation layer during the filling of the conductive material.

### Claim 4 (depends on 2)

The substrate processing method of claim 2, wherein at least one hole connected to the sacrificial layer is generated during the generating of the interlayer insulating layer, and
wherein a conductive protrusion filling the hole is generated during the replacing.

### Claim 5 (depends on 1)

The substrate processing method of claim 1,
wherein the adjacent ones of the conductive word line structures comprise a first stack structure and a second stack structure formed over the first stack structure, and
wherein the first conductive layer of the first stack structure and the second conductive layer of the second stack structure are spaced apart from each other by a height of the separation layer in a vertical direction.

### Claim 6 (depends on 1)

The substrate processing method of claim 1, wherein the second conductive layer comprises a first protrusion protruding from the first conductive layer, and
wherein the first protrusion is in contact with the separation layer.

### Claim 7 (depends on 6)

The substrate processing method of claim 6, wherein the separation layer has a spacer shape, and
wherein a lower surface of the second conductive layer has a profile corresponding to the spacer shape.

### Claim 8 (depends on 6)

The substrate processing method of claim 6, wherein the second conductive layer further comprises a second protrusion protruding from an end of the first protrusion in a downward direction.

### Claim 9 (depends on 6)

The substrate processing method of claim 6, wherein the second conductive layer comprises:
a first region overlapped with the first conductive layer; and
a second region overlapped with the separation layer.

### Claim 10 (depends on 9)

The substrate processing method of claim 9, wherein a via contact in contact with the conductive word line structure is generated, and
wherein the via contact is in contact with the first and second regions of the second conductive layer.

### Claim 11 (depends on 1)

The substrate processing method of claim 1, wherein the generating of the separation layer comprises:
generating a first layer on the stair structure, the first layer comprising a first portion disposed on each of the plurality of side surfaces of the stair structure and a second portion disposed on each of a plurality of upper surfaces of the stair structure;
selectively densifying the first layer by applying a first energy in such a manner that the first portion is more densified than the second portion; and
isotropically etching the first layer to remove the second portion of the first layer to leave the first portion of the first layer.

### Claim 12 (depends on 2)

The substrate processing method of claim 2, wherein the generating of the pad layer comprises:
generating a second layer on the stair structure, the second layer comprising a first portion disposed on each of the plurality of side surfaces of the stair structure and a second portion disposed on each of a plurality of upper surfaces of the stair structure;
selectively densifying the second layer by applying a second energy in such a manner that the second portion of the second layer is more densified than the first portion of the second layer; and
isotropically etching the second layer to remove the first portion of the second layer to leave the second portion of the second layer.

### Claim 13 (depends on 11)

The substrate processing method of claim 11, wherein the first energy is equal to or higher than a preset threshold, and weakens the second portion of the first layer.

### Claim 14

A semiconductor device comprising:
a substrate;
at least one memory cell string protruding and extending in an upward direction from the substrate;
a first word line formed over the substrate and connected to a first memory cell of the memory cell string;
a second word line formed over the first word line and connected to a second memory cell of the memory cell string;
an insulating layer interposed between the first word line and the second word line, the insulating layer comprising a plurality of side surfaces; and
a separation layer disposed on each of the plurality of the side surfaces of the insulating layer,
wherein each of the first and second word lines comprises:
a first conductive layer extending toward a channel; and
a second conductive layer provided on the first conductive layer,
wherein at least a part of a side surface of the first conductive layer of the second word line is in contact with the separation layer, and
wherein the second conductive layer comprises a first protrusion protruding from the first conductive layer in a horizontal direction.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the second conductive layer further comprises a second protrusion protruding from an end of the first protrusion in a downward direction.