# US 10,504,900 B2 · Enhanced field Resistive RAM integrated with nanosheet technology

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- Number: US 10,504,900 B2
- Document ID: US10504900B2
- Status: Granted
- Kind: B2
- Application number: 15/960,092
- Filed: 2018-04-23
- Published: 2019-10-24
- Granted: 2019-12-10
- Earliest claimed: 2018-04-23
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Pouya Hashemi; Takashi Ando; Alexander Reznicek
- Web page: https://patentgrep.com/patent/US10504900B2

## CPC

- H10D 62/121: {oriented parallel to substrates}
- H10D 84/853: {comprising FinFETs}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10B 63/34: {of the vertical channel field-effect transistor type}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10N 70/253: {having three or more electrodes, e.g. transistor-like devices}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A semiconductor structure containing a resistive random access memory device integrated with a gate-all-around nanosheet CMOS device is provided. In one embodiment, the semiconductor structure includes a gate-all-around nanosheet CMOS device includes a functional gate structure present on, and between, each semiconductor channel material nanosheet of a nanosheet stack of suspended semiconductor channel material nanosheets. The structure of the present application further includes a resistive memory device located laterally adjacent to the gate-all-around nanosheet CMOS device that includes a second functional gate structure present on, and between, each recessed semiconductor channel material layer portion of a material stack, wherein a recessed sacrificial semiconductor material layer portion is located above and below each recessed semiconductor channel material layer portion. A shared source/drain region is located between the gate-all-around nanosheet CMOS device and the resistive memory device.

## Claims

### Claim 1

A semiconductor structure comprising:
a gate-all-around nanosheet complementary metal-oxide-semiconductor (CMOS) device comprising a first functional gate structure present on, and between two adjacent semiconductor channel material nanosheets of a nanosheet stack of suspended semiconductor channel material nanosheets;
a resistive memory device located laterally adjacent to the gate-all-around nanosheet CMOS device and comprising a second functional gate structure present on, and between two adjacent recessed semiconductor channel material layer portions of a material stack, wherein a recessed sacrificial semiconductor material layer portion is located above and below each of the recessed semiconductor channel material layer portions; and
a shared source/drain (S/D) region located between the gate-all-around nanosheet CMOS device and the resistive memory device.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein an S/D junction is located between each of the semiconductor channel material nanosheets and the shared S/D region, and between each of the recessed semiconductor channel material layer portions and the shared S/D region.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein the recessed semiconductor channel material layer portions have sharp corners that facilitate electroforming of a filament of the resistive memory device.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein each of the recessed semiconductor channel material layer portions has a width that is greater than a width of the sacrificial semiconductor material layer portion.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, further comprising a first gate spacer located above the nanosheet stack of the suspended semiconductor channel material nanosheets and surrounding an upper portion of the first functional gate structure, and an inner spacer surrounding other portions of the first functional gate structure.

### Claim 6 (depends on 5)

The semiconductor structure of claim 5, further comprising a second gate spacer located above the material stack and surrounding an upper portion of the second functional gate structure, and an inner spacer surrounding a sidewall of other portions of the second functional gate structure.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, further comprising an S/D region located on a side of the first gate structure not containing the shared S/D region, wherein an S/D junction is present between the S/D region and sidewalls of each of the semiconductor channel material nanosheets.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, further comprising an interlayer dielectric (ILD) material laterally surrounding and present atop the first and second functional gate structures.

### Claim 9 (depends on 8)

The semiconductor structure of claim 8, further comprising an S/D contact structure present in the ILD material and directly contacting a topmost surface of the shared S/D region, a first gate contact structure present in the ILD material and directly contacting the first functional gate structure, a second gate contact structure present in the ILD material and directly contacting the second functional gate structure, and a dummy contact structure present in the ILD material and directly contacting a topmost surface of the material stack.

### Claim 10 (depends on 1)

The semiconductor structure of claim 1, wherein the semiconductor channel material nanosheets and the recessed semiconductor channel material layer portions comprise a different semiconductor material than the recessed sacrificial semiconductor material layer portion.

### Claim 11 (depends on 10)

The semiconductor structure of claim 10, wherein the semiconductor channel material nanosheets and the recessed semiconductor channel material layer portions are composed of silicon and the recessed sacrificial semiconductor material layer portion is composed is a silicon germanium alloy.