# US 10,504,899 B2 · Transistors with various threshold voltages and method for manufacturing the same

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- Number: US 10,504,899 B2
- Document ID: US10504899B2
- Status: Granted
- Kind: B2
- Application number: 15/853,542
- Filed: 2017-12-22
- Published: 2019-05-30
- Granted: 2019-12-10
- Earliest claimed: 2017-11-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Jhon-Jhy Liaw
- Web page: https://patentgrep.com/patent/US10504899B2

## CPC

- H10D 84/853: {comprising FinFETs}
- H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/105: {by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] (IGFETs having LDD or drain extension regions H10D30/601)}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 10/011: {of isolation regions comprising dielectric materials}
- H10W 10/10: Isolation regions comprising dielectric materials
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a first circuit and a second circuit. The first circuit includes a first gate, a first drain, and a first source. The second circuit includes a second gate, a second drain, and a second source. The first drain and the first source of the first circuit include a first doping material with a first concentration. A gate pitch and a gate critical dimension of the first gate of the first circuit are the same as a gate pitch and a gate critical dimension of the second gate of the second circuit. The second drain and the second source of the second circuit include a second doping material with a second concentration, wherein the first concentration is different from the second concentration.

## Claims

### Claim 1

A semiconductor device, comprising:
a first circuit, comprising:
a first gate,
a first drain, comprising a first doping material with a first concentration; and
a first source, comprising the first doping material with the first concentration; and
a second circuit, comprising:
a second gate, wherein a gate pitch and a gate critical dimension of the first gate are the same as a gate pitch and a gate critical dimension of the second gate;
a second drain, comprising a second doping material with a second concentration; and
a second source, comprising the second doping material with the second concentration, wherein the first concentration is different from the second concentration.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a difference between the first concentration and the second concentration is about 30-50%.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the first drain, the first source, the second drain, and the second source are composed of SiGe, wherein boron is doped into the first drain, the first source, the second drain, and the second source, and a concentration which the boron is doped into the first drain and the first source of the first circuit is the first concentration, and a concentration which the boron is doped into the second drain and the second source of the second circuit is the second concentration.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, wherein the first drain, the first source, the second drain, and the second source are composed of Si, wherein phosphorous is doped into the first drain, the first source, the second drain, and the second source, and a concentration which the phosphorous is doped into the first drain and the first source of the first circuit is the first concentration, and a concentration which the phosphorous is doped into the second drain and the second source of the second circuit is the second concentration.

### Claim 5 (depends on 2)

The semiconductor device of claim 2, wherein the first circuit is disposed adjacent to the second circuit.

### Claim 6 (depends on 2)

The semiconductor device of claim 2, further comprising:
a shallow trench isolation disposed between the first circuit and the second circuit for isolating the first circuit and the second circuit.

### Claim 7 (depends on 2)

The semiconductor device of claim 2, wherein the first circuit and the second circuit comprise at least one of P-type transistor and N-type transistor.

### Claim 8 (depends on 2)

The semiconductor device of claim 2, wherein the first circuit and the second circuit comprise single fin-line fin field effect transistors (FET).

### Claim 9

A semiconductor device, comprising:
a substrate;
a well, forming on the substrate;
a first transistor formed in the well, comprising:
a first gate region;
a first heavy doped drain region; and
a first heavy doped source region, wherein a doping concentration of the first heavy doped drain region and the first heavy doped source region is a first concentration; and
a second transistor formed in the well and disposed adjacent to the first transistor, comprising:
a second gate region, wherein a gate pitch and a gate critical dimension of the second gate region are the same as a gate pitch and a gate critical dimension of the first gate region;
a second doped drain region; and
a second doped source region, wherein a doping concentration of the second doped drain region and the second doped source region is a second concentration, wherein a difference between the first concentration and the second concentration is about 30-50%.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the first heavy doped drain region and the first heavy doped source region are formed of SiGe, and boron is doped into the first heavy doped drain region and the first heavy doped source region.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein the first heavy doped drain region and the first heavy doped source region are formed of Si, and phosphorous is doped into the first heavy doped drain region and the first heavy doped source region.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, further comprising:
a shallow trench isolation disposed between the first transistor and the second transistor for isolating the first transistor and the second transistor.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, wherein the first transistor and the second transistor comprise at least one of P-type transistor and N-type transistor.

### Claim 14 (depends on 9)

The semiconductor device of claim 9, wherein the first transistor and the second transistor comprise single fin-line fin field effect transistors (FET).

### Claim 15

A method, comprising:
forming a well on a substrate;
forming a first transistor in the well, comprising:
forming a first gate region;
forming a first heavy doped drain region; and
forming a first heavy doped source region, wherein a doping concentration of the first heavy doped drain region and the first heavy doped source region is a first concentration;
forming a second transistor in the well and disposing the second transistor adjacent to the first transistor, comprising:
forming a second gate region, wherein a gate pitch and a gate critical dimension of the second gate region are the same as a gate pitch and a gate critical dimension of the first gate region;
forming a second doped drain region; and
forming a second doped source region, wherein a doping concentration of the second doped drain region and the second doped source region is a second concentration, wherein a difference between the first concentration and the second concentration is about 30-50%.

### Claim 16 (depends on 15)

The method of claim 15, wherein the first heavy doped drain region and the first heavy doped source region are formed of SiGe, and boron is doped into the first heavy doped drain region and the first heavy doped source region.

### Claim 17 (depends on 15)

The method of claim 15, wherein the first heavy doped drain region and the first heavy doped source region are formed of Si, and phosphorous is doped into the first heavy doped drain region and the first heavy doped source region.

### Claim 18 (depends on 15)

The method of claim 15, further comprising:
forming a shallow trench isolation disposed between the first transistor and the second transistor for isolating the first transistor and the second transistor.

### Claim 19 (depends on 15)

The method of claim 15, wherein the first transistor and the second transistor comprise at least one of P-type transistor and N-type transistor.

### Claim 20 (depends on 15)

The method of claim 15, wherein the first transistor and the second transistor comprise single fin-line fin field effect transistors (FET).