# US 10,504,896 B2 · HVMOS reliability evaluation using bulk resistances as indices

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- Number: US 10,504,896 B2
- Document ID: US10504896B2
- Status: Granted
- Kind: B2
- Application number: 15/995,778
- Filed: 2018-06-01
- Published: 2018-09-27
- Granted: 2019-12-10
- Earliest claimed: 2011-05-19
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chi-Feng Huang; Chia-Chung Chen; Tse-Hua Lu
- Web page: https://patentgrep.com/patent/US10504896B2

## CPC

- H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics}
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 89/10: Integrated device layouts
- H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers}
- G01R 27/08: Measuring resistance by measuring both voltage and current
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 62/378: {Contact regions to the substrate regions}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance.

## Claims

### Claim 1

A structure comprising:
a semiconductor substrate;
a plurality of High-Voltage P-type Metal-Oxide-Semiconductor (HVPMOS) devices formed at a surface of the semiconductor substrate, wherein the plurality of HVPMOS devices form an array comprising a plurality of rows and a plurality of columns; and
an n-type guard ring comprising a plurality of portions, each encircling one of the plurality of HVPMOS devices, with neighboring ones of the plurality of HVPMOS devices separated from each other by the n-type guard ring.

### Claim 2 (depends on 1)

The structure of claim 1 further comprising a plurality of isolation regions separated from each other by the n-type guard ring, and each of the plurality of HVPMOS devices comprises an active region encircled by one of the plurality of isolation regions.

### Claim 3 (depends on 2)

The structure of claim 2, wherein the plurality of isolation regions comprise an isolation region encircled by one of the plurality of portions, with no High-Voltage N-type Metal-Oxide-Semiconductor (HVNMOS) having any active region that is also encircled by the isolation region.

### Claim 4 (depends on 3)

The structure of claim 3, wherein each of the plurality of portions encircles an active region of a single HVPMOS device, and no active region of any additional MOS device is encircled by any of the plurality of isolation regions.

### Claim 5 (depends on 2)

The structure of claim 2, wherein the active region of the each of the plurality of HVPMOS devices has an active-region-to-guard-ring spacing smaller than about 2 μm, and the active-region-to-guard-ring spacing is between the active region and a nearest portion of the n-type guard ring.

### Claim 6 (depends on 1)

The structure of claim 1, wherein a region encircled by the n-type guard ring has a length and a width smaller than the length, with the width being smaller than about 30 μm.

### Claim 7 (depends on 6)

The structure of claim 6, wherein the width is measured in a direction perpendicular to lengthwise directions of active regions of the plurality of HVPMOS devices.

### Claim 8 (depends on 1)

The structure of claim 1 further comprising a High-Voltage N-type Metal-Oxide-Semiconductor (HVNMOS) device encircled by an additional guard ring, wherein the HVNMOS device has an additional active-region-to-guard-ring spacing greater than 2 μm.

### Claim 9 (depends on 8)

The structure of claim 8, wherein the HVNMOS device comprises an active region encircled by an additional isolation region, and no addition MOS device has any active region encircled by the additional isolation region.

### Claim 10 (depends on 1)

The structure of claim 1, wherein the n-type guard-ring comprises a portion of the semiconductor substrate that are heavily doped as n-type.

### Claim 11

A structure comprising:
a semiconductor substrate;
a heavily doped semiconductor region extending into the semiconductor substrate wherein the heavily doped semiconductor region forms a guard ring;
a plurality of isolation regions extending into the semiconductor substrate and forming an array, wherein each of the plurality of isolation regions is separated from other ones of the plurality of isolation regions by the heavily doped semiconductor region;
a plurality of active regions, each encircled by one of the plurality of isolation regions, wherein the plurality of active regions have active-region-to-guard-ring spacings smaller than about 2 pm; and
a plurality of High-Voltage P-type Metal-Oxide-Semiconductor (HVPMOS) devices formed based on the plurality of active regions.

### Claim 12 (depends on 11)

The structure of claim 11, wherein each of the plurality of isolation regions encircles a single active region.

### Claim 13 (depends on 11)

The structure of claim 11, wherein the heavily doped semiconductor region forms a plurality of rings that are interconnected with each other, and inside each of the plurality of rings, a single one of the plurality of HVPMOS devices is formed.

### Claim 14 (depends on 11)

The structure of claim 11, wherein each of the plurality of isolation regions has a length and a width smaller than the length, with the width being smaller than about 30 μm.

### Claim 15 (depends on 11)

The structure of claim 11 further comprising a High-Voltage N-type Metal-Oxide-Semiconductor (HVNMOS) device encircled by an additional heavily doped semiconductor region, wherein the HVNMOS device has an additional active-region-to-guard-ring spacing greater than 2 μm.

### Claim 16 (depends on 11)

The structure of claim 11, wherein the heavily doped semiconductor region has an n-type impurity concentration higher than about 1×1019/cm3.

### Claim 17

A structure comprising:
a semiconductor substrate;
a heavily doped semiconductor region extending into the semiconductor substrate, wherein the heavily doped semiconductor region is of n-type;
a plurality of Shallow Trench Isolation (STI) regions extending into the semiconductor substrate and forming an array, wherein each of the plurality of STI regions is separated from other ones of the plurality of STI regions by the heavily doped semiconductor region;
a plurality of active regions, each encircled by one of the plurality of STI regions, wherein each of the plurality of STI regions has a rectangular top-view shape, and has a length and a width smaller than the length, with the width being smaller than about 30 μm; and
a plurality of High-Voltage P-type Metal-Oxide-Semiconductor (HVPMOS) devices, each being formed based on one of the plurality of active regions.

### Claim 18 (depends on 17)

The structure of claim 17, wherein each of the plurality of STI regions encircles a single active region.

### Claim 19 (depends on 17)

The structure of claim 17, wherein the heavily doped semiconductor region forms a plurality of rings that are interconnected with each other to form a continuous semiconductor region, and inside each of the plurality of rings, a single one of the plurality of HVPMOS devices is formed.

### Claim 20 (depends on 17)

The structure of claim 17, wherein the heavily doped semiconductor region has an n-type impurity concentration higher than about 1×1019/cm3.