# US 10,504,895 B2 · FinFET isolation structure and method for fabricating the same

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- Number: US 10,504,895 B2
- Document ID: US10504895B2
- Status: Granted
- Kind: B2
- Application number: 15/414,413
- Filed: 2017-01-24
- Published: 2017-05-18
- Granted: 2019-12-10
- Earliest claimed: 2015-11-12
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Che-Cheng Chang; Chih-Han Lin
- Web page: https://patentgrep.com/patent/US10504895B2

## CPC

- H10D 84/834: {comprising FinFETs}
- H10D 30/0217: {forming self-aligned punch-through stoppers or threshold implants under gate regions}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 62/112: {for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10W 10/021: {of air gaps}
- H10W 10/20: Air gaps
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a semiconductor substrate, a first semiconductor fin, a second semiconductor fin, an air gap and a dielectric cap layer. The first semiconductor fin is disposed on the semiconductor substrate, and the second semiconductor fin is disposed on the semiconductor substrate. The air gap is located between the first semiconductor fin and the second semiconductor fin, and the dielectric cap layer caps a top of the air gap.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor substrate;
a first semiconductor fin on the semiconductor substrate;
a second semiconductor fin on the semiconductor substrate;
an air gap between the first semiconductor fin and the second semiconductor fin;
a dielectric cap layer capping a top of the air gap; and
two dummy gate spacers respectively on the first semiconductor fin and the second semiconductor fin, and sandwiching the dielectric cap layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first semiconductor fin and the second semiconductor fin are spaced at a distance substantially in a range from 5 nm to 50 nm.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the dielectric cap layer comprises silicon oxide or silicon nitride.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further comprising:
a stop layer disposed between the semiconductor substrate, and the first semiconductor fin and the second semiconductor fin.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the stop layer comprises SiGeOx, SiGe, SiOx, SiP or SiPOx, where x is greater than 0.

### Claim 6 (depends on 4)

The semiconductor device of claim 4, wherein the stop layer has a thickness substantially in a range from 1 nm to 50 nm.

### Claim 7 (depends on 4)

The semiconductor device of claim 4, wherein the air gap has a first air gap on the stop layer, and a second air gap above the first air gap, and a width of a bottom of the first air gap is greater than a width of a bottom of the second air gap.

### Claim 8 (depends on 4)

The semiconductor device of claim 4, where the air gap extends from tops of the first semiconductor fin and the second semiconductor fin to a portion of the semiconductor substrate through the stop layer.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the air gap has a flat bottom enclosed by an arc surface, and a width of the flat bottom of the air gap is smaller than a width of a top of the dielectric cap layer.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the air gap extends between a portion of the dummy gate spacers.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, comprising:
an epitaxial layer, wherein the epitaxial layer is spaced apart from the air gap by the first semiconductor fin.

### Claim 12

A semiconductor device, comprising:
a semiconductor substrate; a stop layer on the semiconductor substrate;
a first semiconductor fin on the stop layer; a second semiconductor fin on the stop layer;
a first dummy gate spacer overlying the first semiconductor fin; a second dummy gate spacer overlying the second semiconductor fin; and a dielectric cap layer between the first dummy gate spacer and the second dummy gate spacer, wherein a bottom of the dielectric cap layer is separated from the stop layer.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the first semiconductor fin and the second semiconductor fin are spaced at a distance substantially in a range from 5 nm to 50 nm.

### Claim 14 (depends on 12)

The semiconductor device of claim 12, wherein the stop layer has a thickness substantially in a range from 1 nm to 50 nm.

### Claim 15

A method for forming a semiconductor device, the method comprising:
forming a dummy gate at least on a top of a semiconductor fin;
forming at least one dummy gate spacer on at least one sidewall of the dummy gate;
etching the dummy gate and the semiconductor fin to form an air gap dividing the semiconductor fin into first and second portions; and
forming a dielectric cap layer into the air gap to cap a top of the air gap.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
forming a stop layer between a semiconductor substrate and the semiconductor fin.

### Claim 17 (depends on 16)

The method of claim 16, wherein etching the dummy gate and the semiconductor fin further etches the stop layer and a portion of semiconductor fin.

### Claim 18 (depends on 16)

The method of claim 16, wherein an operation of etching etches the stop layer by using CxFy, NFx, N2, O2, CL2, Ar, SFx, CxHyFz or HBr as an etchant, where x and y are greater than 0.

### Claim 19 (depends on 16)

The method of claim 16, wherein forming the stop layer is performed by implantation or atomic layer deposition (ALD).

### Claim 20 (depends on 15)

The method of claim 15, wherein forming the dielectric cap layer is performed using silicon oxide or silicon nitride.