# US 10,504,892 B2 · Semiconductor device

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- Number: US 10,504,892 B2
- Document ID: US10504892B2
- Status: Granted
- Kind: B2
- Application number: 16/018,616
- Filed: 2018-06-26
- Published: 2018-10-25
- Granted: 2019-12-10
- Earliest claimed: 2015-11-02
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Jia-Rui Lee; Kuo-Ming Wu; Yi-Chun Lin; Alexander Kalnitsky
- Web page: https://patentgrep.com/patent/US10504892B2

## CPC

- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 30/0281: {of lateral DMOS [LDMOS] FETs}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10D 84/0144: {Manufacturing their gate insulating layers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83125: {the IGFETs characterised by having shared source or drain regions}
- H10D 84/8314: {the IGFETs characterised by having gate insulating layers with different properties}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 64/514: {characterised by the insulating layers}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0156: {Manufacturing their doped wells}
- H10D 84/835: {comprising LDMOS}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device of a circuit is provided. The circuit is configured to be operated under a power supply. The semiconductor device of the circuit includes a first transistor and a second transistor. The first transistor includes a first source region in a first bulk region; a first drain region defined by a well and a doped region, wherein the first source region and the doped region are separate by a distance, which is a factor which determines a breakdown voltage of the first transistor, the breakdown voltage being associated with the power supply; and a first gate. The second transistor includes a second source region in a second bulk region, the second source region electrically connected with the first source region and the first gate.

## Claims

### Claim 1

A semiconductor device, comprising:
a first transistor including:
a first source region; and
a first gate; and
a second transistor including:
a second source region electrically connected with the first source region and the first gate,
wherein the second transistor has a threshold voltage greater than that of the first transistor.

### Claim 2 (depends on 1)

The semiconductor device as claimed in claim 1,
wherein the first transistor further includes:
a first insulating layer, on a first channel of the first transistor, being a factor which determines the threshold voltage of the first transistor, and
wherein the second transistor further includes:
a second insulating layer, on a second channel of the second transistor, being a factor which determines the threshold voltage of the second transistor,
wherein a thickness of the second insulating layer is greater than that of the first insulating layer.

### Claim 3 (depends on 2)

The semiconductor device as claimed in claim 2, wherein the first source region is in a first bulk region, and the second source region is in a second bulk region, wherein the first bulk region has a first dopant concentration, and the second bulk region has a second dopant concentration higher than the first dopant concentration.

### Claim 4 (depends on 2)

The semiconductor device as claimed in claim 2, wherein the first source region is in a first bulk region, and the second source region is in a second bulk region, wherein the first bulk region has a first dopant concentration, and the second bulk region has a second dopant concentration equal to the first dopant concentration.

### Claim 5 (depends on 1)

The semiconductor device as claimed in claim 1,
wherein the first source region is in a first bulk region, the first bulk region having a first concentration which is a factor which determines the threshold voltage of the first transistor, and
wherein the second source region is in a second bulk region, the second bulk region having a second concentration which is a factor which determines the threshold voltage of the second transistor,
wherein the second concentration is higher than the first concentration.

### Claim 6 (depends on 5)

The semiconductor device as claimed in claim 5,
wherein the first transistor further includes:
a first insulating layer on a first channel of the first transistor; and
a first gate on the first insulating layer, and
wherein the second transistor further includes:
a second insulating layer on a second channel of the second transistor; and
a second gate on the second insulating layer,
wherein a thickness of the second insulating layer is greater than that of the first insulating layer.

### Claim 7 (depends on 5)

The semiconductor device as claimed in claim 5,
wherein the first transistor further includes:
a first insulating layer on a first channel of the first transistor; and
a first gate on the first insulating layer, and
wherein the second transistor further includes:
a second insulating layer on a second channel of the second transistor; and
a second gate on the second insulating layer,
wherein a thickness of the second insulating layer is equal to that of the first insulating layer.

### Claim 8 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the first transistor further includes a first drain region defined by a well and a doped region, and the second transistor includes a second drain region defined by the well and the doped region.

### Claim 9 (depends on 8)

The semiconductor device as claimed in claim 8, wherein the first source region and the doped region are separate.

### Claim 10 (depends on 9)

The semiconductor device as claimed in claim 9, further comprising:
a first shallow trench isolation (STI) and a second STI, wherein the doped region is between the first and second STIs.

### Claim 11 (depends on 3)

The semiconductor device as claimed in claim 3, wherein the first bulk region overlaps a portion of the first gate and the second bulk region overlaps a portion of a second gate of the second transistor, the semiconductor device further comprising:
a first channel defined in the first bulk region and a second channel defined in the second bulk region.

### Claim 12

A semiconductor device, comprising:
a first transistor including:
a first source region; and
a first gate; and
a second transistor including:
a second source region electrically connected with the first source region and the first gate,
a second drain region in combination with the second source region defining a body diode therebetween,
wherein a threshold voltage of the body diode is greater than that of the first transistor.

### Claim 13 (depends on 12)

The semiconductor device as claimed in claim 12,
wherein the first transistor includes:
a first drain region defined by a well and a doped region, wherein the second drain region is defined by the well and the doped region.

### Claim 14 (depends on 13)

The semiconductor device as claimed in claim 13, further comprising:
a first shallow trench isolation (STI) and a second STI, wherein the doped region is between the first and second STIs.

### Claim 15 (depends on 13)

The semiconductor device as claimed in claim 13, further comprising:
a first isolation structure disposed between the doped region and the first source region.

### Claim 16 (depends on 15)

The semiconductor device as claimed in claim 15, wherein the first isolation structure includes a shallow trench isolation.

### Claim 17

A method, comprising:
providing a substrate;
defining a well in the substrate;
forming an insulating layer with a uniform thickness on the substrate;
defining a first bulk region in a first portion of the well;
defining a second bulk region in a second portion of the well, wherein dopant concentration of the second bulk region is greater than the first bulk region;
defining a first source region and a second source region in the first bulk region and the second bulk region, respectively;
forming the first gate over the well; and
connecting the first source region, the first gate and the second source region together.

### Claim 18 (depends on 17)

The semiconductor device as claimed in claim 17, further comprising:
exposing a portion of the first bulk region;
exposing a portion of the second bulk region; and
the defining a first source region and a second source region in the first bulk region and the second bulk region, respectively including:
defining the first source region in the portion of the first bulk region; and
defining the second source region in the portion of the second bulk region.

### Claim 19 (depends on 17)

The semiconductor device as claimed in claim 17, further comprising:
forming a first shallow trench isolation (STI) and a second STI in the substrate; and
forming a doped region in the well between the first and second STIs.

### Claim 20 (depends on 17)

The semiconductor device as claimed in claim 17, wherein the first bulk region overlaps a portion of the insulating layer and the second bulk region overlaps another portion of the insulating layer.