# US 10,504,891 B2 · Semiconductor device and a manufacturing method therefor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,504,891 B2 - Document ID: US10504891B2 - Status: Granted - Kind: B2 - Application number: 16/058,728 - Filed: 2018-08-08 - Published: 2019-02-14 - Granted: 2019-12-10 - Earliest claimed: 2017-08-09 - Assignees: Infineon Technologies Austria AG - Applicants: Infineon Technologies Austria AG - Inventors: Joachim Weyers; Franz Hirler; Maximilian Treiber - Web page: https://patentgrep.com/patent/US10504891B2 ## CPC - H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors} - H10D 1/692: {Electrodes} - H10D 12/441: {Vertical IGBTs} - H10D 12/461: {having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions} - H10D 30/66: Vertical DMOS [VDMOS] FETs - H10D 30/665: {having edge termination structures} - H10D 62/105: {by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] (IGFETs having LDD or drain extension regions H10D30/601)} - H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures} - H10D 62/124: {Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions} - H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)} - H10D 62/8171: {Doping structures, e.g. doping superlattices or nipi superlattices} - H10D 62/8181: {Structures having no potential periodicity in the vertical direction, e.g. lateral superlattices or lateral surface superlattices [LSS]} - H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode} - H10D 64/519: {characterised by their top-view geometrical layouts} - H10D 84/141: {VDMOS having built-in components} - H10D 84/148: {the built-in components being breakdown diodes, e.g. Zener diodes} - H10D 89/611: {using diodes as protective elements} - H10W 20/496: {Capacitor integral with wiring layers} - H10D 64/112: {comprising multiple field plate segments} - H10D 64/23: Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device includes a semiconductor body having first and second opposing sides, an active area, and an inactive area which is, in a projection onto to the first and/or second side, arranged between the active area and an edge of the semiconductor body. A transistor structure in the active area includes a source region adjacent the first side and forms a first pn-junction in the semiconductor body. A gate electrode insulated from the semiconductor body is arranged adjacent to the first pn-junction. A capacitor in the inactive area includes first and second conductors arranged over each other on the first side. A source contact structure arranged above the capacitor is in Ohmic connection with the source region and the first conductor. A gate contact structure is arranged above the capacitor, spaced apart from the source contact structure and in Ohmic connection with the gate electrode and the second conductor. ## Claims ### Claim 1 A semiconductor device, comprising: a semiconductor body comprising a first side and a second side opposite the first side; an active area; an inactive area which is, in a projection onto to the first side, adjacent to the active area; a transistor structure formed in the active area and comprising a source region adjacent to the first side and forming in the semiconductor body a first pn-junction; and a gate electrode insulated from he semiconductor body and arranged adjacent to the first pn-junction; a capacitor formed in the inactive area and comprising a first conductor and a second conductor which are arranged over each other on the first side; a source contact structure arranged, in a vertical direction at least substantially perpendicular to the first side and/or the second side, above the capacitor and in Ohmic connection with the source region and the first conductor; and a gate contact structure arranged in the vertical direction above the capacitor, spaced apart from the source contact structure and in Ohmic connection with the gate electrode and the second conductor. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein a distance between the first conductor and the second conductor is less than about 200 nm. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein at least one of the first conductor and the second conductor overlaps in the projection with at least one of the source contact structure and the gate contact structure, and/or wherein the gate contact structure comprises at least one of a gate pad, a gate runner and a gate field plate arranged in the inactive area and/or at least substantially surrounding the source contact structure in the projection. ### Claim 4 (depends on 1) The semiconductor device of claim 1, further comprising at least one of: a body region disposed in the semiconductor body and forming the first pn-junction with the source region; a drift region disposed in the semiconductor body and forming a second pn-junction with the body region; a drain region disposed in the semiconductor body and in Ohmic connection with the drift region; a plurality of compensation regions, each of the compensation regions forming a pn-junction with a respective portion of the drift region; a drain terminal arranged on the second side and in Ohmic connection with at least one of the drift region and the drain region; and a drain line and/or a drain field plate in Ohmic connection with the drain terminal, arranged on the first side and in the inactive area, and/or in the projection at least substantially surrounding the source contact structure, the gate field plate and/or the gate contact structure. ### Claim 5 A semiconductor device, comprising: a semiconductor body comprising a first side defining a vertical direction, and a second side opposite the first side; an active area; an inactive area which is, in a projection onto to the first side, adjacent to the active area; a dielectric structure arranged on the first side; a source terminal formed on the dielectric structure; a gate terminal formed on the dielectric structure; a transistor cell formed in the active area and comprising a source region in Ohmic connection with the source terminal overlapping with the source region in the projection, and disposed in the semiconductor body, and a gate electrode insulated from the semiconductor body, in Ohmic connection with the gate terminal, and overlapping with the source terminal in the projection; and a capacitor formed in the inactive area, embedded in the dielectric structure, and comprising a first conductor in Ohmic connection with the source terminal and a second conductor in Ohmic connection with the gate terminal, wherein a distance in the vertical direction between the first conductor and the second conductor is less than about 200 nm. ### Claim 6 (depends on 5) The semiconductor device of claim 5, further comprising at least one of: a body region disposed in the semiconductor body and forming a first pn-junction with the source region; a drift region disposed in the semiconductor body and forming a second pn-junction with the body region; a plurality of compensation regions, each of the compensation regions forming a pn-junction with a respective portion of the drift region; a drain region disposed in the semiconductor body and in Ohmic connection with the drift region; a drain terminal arranged on the second side and in Ohmic connection with at least one of the drift region and the drain region; a gate field plate adjoining the gate terminal, arranged in the inactive area spaced apart from the source terminal and/or the source field plate, and/or at least substantially surrounding the source terminal in the projection; and a drain line and/or a drain field plate in Ohmic connection with the drain terminal, arranged on the first side and in the inactive area, and/or in the projection at least substantially surrounding the source terminal, the gate field plate and/or the gate terminal. ### Claim 7 (depends on 5) The semiconductor device of claim 5, wherein the capacitor at least partly bridges a gap between the source contact structure and the gate contact structure, wherein the capacitor is at least partly arranged underneath the gate contact structure, wherein the capacitor is at least partly arranged underneath an edge termination structure, wherein the capacitor overlaps in the projection with an edge termination structure, wherein at least one of the second conductor and the first conductor is implemented as a respective conductive plate, wherein the capacitor comprises a dielectric medium arranged between the first conductor and the second conductor, wherein the dielectric medium adjoins and/or is provided by a first isolation layer of the dielectric structure, and/or wherein the dielectric medium adjoins and/or is provided by a second isolation layer of the dielectric structure which is arranged on the first isolation layer. ### Claim 8 (depends on 5) The semiconductor device of claim 5, wherein the first conductor and the gate electrode are formed by a contiguous conductive layer arranged on the first side. ### Claim 9 (depends on 5) The semiconductor device of claim 5, wherein the second conductor is arranged above the first conductor. ### Claim 10 (depends on 5) The semiconductor device of claim 5, wherein at least one of the first conductor and the second conductor comprises a non-monocrystalline semiconductor material. ### Claim 11 (depends on 5) The semiconductor device of claim 5, wherein a capacitance of the capacitor is at least 10% of a gate-source capacitance of the active area. ### Claim 12 (depends on 5) The semiconductor device of claim 5, wherein a capacitance of the capacitor is larger than about 30 pF. ### Claim 13 (depends on 5) The semiconductor device of claim 5, wherein a specific capacitance of the capacitor is larger than about 170 pF/mm2. ### Claim 14 (depends on 5) The semiconductor device of claim 5, wherein the active area has in the projection a surface area of at most about 50 mm2. ### Claim 15 (depends on 5) The semiconductor device of claim 5, wherein the capacitor overlaps in the projection with at least one of a gap arranged between the source terminal and the gate terminal, the source terminal, the gate terminal and the gate field plate. ### Claim 16 (depends on 15) The semiconductor device of claim 15, further comprising an electrostatic discharge protection structure formed in the inactive area, formed on the first side, embedded in the dielectric structure, bridging the gap and/or overlapping with the gap. ### Claim 17 (depends on 5) The semiconductor device of claim 5, wherein the active area comprises a plurality of transistor cells, wherein the inactive area at least partly surrounds the active area in the projection, and/or wherein the inactive area comprises a peripheral area which is, in a projection onto to the first side and/or the second side, arranged between the active area and an edge of the semiconductor body. ### Claim 18 (depends on 5) The semiconductor device of claim 5, wherein the semiconductor device is implemented as a MOSFET, wherein the semiconductor device is implemented as an IGBT, wherein the semiconductor device is implemented as a power semiconductor device, and/or wherein the semiconductor device is implemented as a charge compensation semiconductor device. ### Claim 19 A method for manufacturing a semiconductor device comprising a transistor, the method comprising: providing a semiconductor body comprising a first side, a second side opposite the first side, an active area, an inactive area being, in a projection onto a horizontal plane substantially parallel to the first side and/or the second side, adjacent to the active area, and a source region adjacent to the first side, and extending to a first pn-junction arranged in the active area; forming a dielectric structure comprising two embedded conductive layers on the first side so that a first layer of the two conductive layers is arranged in the inactive area and that a second layer of the two conductive layers comprises a first portion forming a gate electrode overlapping in the projection onto the horizontal plane with the first pn-junction, and a second portion spaced apart from and overlapping in the projection onto the horizontal plane with the first conductive layer so that a vertical distance between the first conductive layer and the second portion is less than about 200 nm; and forming on the dielectric structure a source terminal in Ohmic connection with the source region and the first layer. ### Claim 20 (depends on 19) The method of claim 19, further comprising at least one of: forming on the dielectric structure a gate terminal in Ohmic connection with the second conductive layer; forming the first layer on a lower dielectric sub-structure of the dielectric structure, the lower dielectric sub-structure comprising a gate dielectric layer in the active area and a field dielectric layer in the inactive area; depositing an intermediate dielectric layer on the first layer; thinning the intermediate dielectric layer above the first layer; forming the second layer; and depositing an upper dielectric layer of the dielectric structure.