# US 10,504,890 B2 · High density nanosheet diodes

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- Number: US 10,504,890 B2
- Document ID: US10504890B2
- Status: Granted
- Kind: B2
- Application number: 15/805,670
- Filed: 2017-11-07
- Published: 2018-04-12
- Granted: 2019-12-10
- Earliest claimed: 2016-10-10
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Kangguo Cheng; Juntao Li; Geng Wang; Qintao Zhang
- Web page: https://patentgrep.com/patent/US10504890B2

## CPC

- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 8/00: Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00)
- H10D 8/045: {of PN junction diodes}
- H10D 8/422: {PN diodes having the PN junctions in mesas}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/0323: {comprising monocrystalline silicon}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6744: {Monocrystalline silicon}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/117: {Shapes of semiconductor bodies}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/128: {Anode regions of diodes}
- H10D 62/129: {Cathode regions of diodes}
- H10D 62/8171: {Doping structures, e.g. doping superlattices or nipi superlattices}
- H10D 84/0109: {the at least one component covered by H10D12/00 or H10D30/00 being a MOS device}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 86/01: Manufacture or treatment
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Embodiments are directed to a method for forming a semiconductor structure by depositing a stack of alternating layers of two materials over a substrate and defining field-effect transistor (FET) and diode regions. The method further includes depositing a mask, where the mask covers only the FET region while leaving the diode region uncovered. The method further includes doping the material in the diode region with a dopant, implanting epitaxial material with another dopant to form PN junctions, stripping the mask from the structure, forming a metal gate conductor over the FET region, and depositing a metal over the substrate to create terminals.

## Claims

### Claim 1

A semiconductor structure, comprising:
a substrate having a field-effect transistor region and a diode region;
a first stack comprising layers of a first material at the field-effect transistor region;
a second stack comprising the layers of the first material alternating with layers of a second material at the diode region, the second material having a first dopant at the diode region, wherein the second material having the first dopant wraps around each of the layers of the first material at the diode region and the second material is directly below a bottommost layer of the layers of the first material at the diode region, wherein the first material at the diode region has a second dopant;
a third material having a third dopant at opposing sidewalls of the second stack, wherein a conductivity type of the first material having the second dopant is the same as a conductivity type of the third material having the third dopant, wherein a conductivity type of the second material having the first dopant is opposite to the conductivity type of the first material having the second dopant and the conductivity type of the third material having the third dopant; and
a metalizing contact material over the substrate, wherein both the field-effect transistor region and the diode region include terminals.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, further comprising a dielectric layer over the substrate.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, wherein the dielectric layer is patterned to form trenches.

### Claim 4 (depends on 3)

The semiconductor structure of claim 3, wherein the metalizing contact material fills the trenches.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein each of the layers of the first material comprises a nanosheet.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein each of the layers of the first material comprises a nanowire.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein the first material comprises silicon (Si).

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, wherein the substrate comprises a semiconductor-on-insulator (SOI) structure.

### Claim 9 (depends on 1)

The semiconductor structure of claim 1, wherein the conductivity type of the second material having the first dopant comprises p-type and wherein each of the conductivity type of the first material having the second dopant and the conductivity type of the third material having the third dopant comprises n-type.