# US 10,504,889 B1 · Integrating a junction field effect transistor into a vertical field effect transistor

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- Number: US 10,504,889 B1
- Document ID: US10504889B1
- Status: Granted
- Kind: B1
- Application number: 16/037,072
- Filed: 2018-07-17
- Granted: 2019-12-10
- Earliest claimed: 2018-07-17
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Brent A. Anderson; Huiming Bu; Terence B. Hook; Xuefeng Liu; Junli Wang
- Web page: https://patentgrep.com/patent/US10504889B1

## CPC

- H10D 84/40: characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/0515: {of vertical FETs having PN homojunction gates}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/831: {Vertical FETs having PN junction gate electrodes (Vertical SIT H10D30/202)}
- H10D 62/122: {oriented at angles to substrates, e.g. perpendicular to substrates}
- H10D 62/149: {Source or drain regions of field-effect devices}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 62/328: {having PN junction gates}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/01324: {characterised by the sectional shape, e.g. T or inverted-T}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/411: {for FETs}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 84/0123: {Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/016: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/80: characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs (H10D84/40 takes precedence)
- H10D 84/82: of only field-effect components
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 62/60: Impurity distributions or concentrations
- H10D 62/834: further characterised by the dopants
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10P 76/405: {characterised by their composition, e.g. multilayer masks}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10P 95/062: {involving a dielectric removal step}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments of the invention include first and second devices formed on a substrate. The first device includes a bottom source or drain (S/D) region, a plurality of fins formed on portions of the bottom S/D region, a bottom spacer formed on the bottom S/D region, a dielectric layer, a gate, a top S/D region formed on each fin of a plurality of fins, and one or more contacts. The dielectric layer is disposed between the gate and the fin of the plurality of fins. The second device includes a bottom doped region, a channel formed the bottom doped region, a sidewall doped region of the channel, a gate coupled to the sidewall doped region, a top doped region, and one or more contacts. A junction is formed between the channel and the sidewall doped region. The cap layer is formed on the gate and the top doped region.

## Claims

### Claim 1

A method of fabricating semiconductor devices, the method comprising:
performing fabrication operations to form a first transistor device on a substrate, wherein the fabrication operations to form the first transistor device comprise:
forming one or more fins on the substrate;
forming a bottom source or drain (S/D) region on the substrate;
forming a bottom spacer on the bottom S/D region;
forming a dielectric layer over the one or more fins;
forming a metal gate for the one or more fins over the dielectric layer;
forming a cap layer over the bottom spacer and metal gate; and
forming a top S/D region over the one or more fins; and
performing fabrication operations to form a second transistor device on the substrate, wherein the fabrication operations to form the second transistor device comprise:
forming a bottom region of the second transistor device on the substrate;
forming the channel region on the bottom region, wherein the one or more fins of the first transistor device are formed with the channel region of the second transistor device;
forming the bottom spacer;
forming sidewalls of the channel region of the second transistor device;
forming a metal gate for the second transistor device, wherein the metal gate for the second transistor device is formed with the metal gate for the one or more fins;
forming the cap layer over bottom spacer and the metal gate of the second transistor device;
forming the top region over the sidewalls and the channel region; and
forming one or more contacts over the top region.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first transistor device comprises a vertical fin field effect transistor (VFET) and the second transistor device comprises a junction field effect transistor (JEFT).

### Claim 3 (depends on 1)

The method of claim 1, wherein the gate of the first semiconductor device and the second semiconductor device is a wrap-around gate.

### Claim 4 (depends on 1)

The method of claim 1, wherein the dielectric layer comprises a high-k dielectric layer.

### Claim 5 (depends on 1)

The method of claim 1, wherein there is no high-k dielectric layer on the JFET gate.

### Claim 6 (depends on 1)

The method of claim 1, wherein a width dimension of the channel region is greater that a width dimension of each of the one or more fins.

### Claim 7 (depends on 1)

The method of claim 1, wherein forming the one or more fins comprises a self-aligned double patterning (SADP) process.

### Claim 8 (depends on 1)

The method of claim 1, wherein forming the channel region of the second transistor comprises a direct lithography process.

### Claim 9 (depends on 1)

The method of claim 1 further comprising forming one or more shallow trench isolation layers between the first transistor device and the second transistor device.

### Claim 10 (depends on 1)

The method of claim 1, wherein:
the channel comprises sidewalls and a main body region; and
the sidewalls of the channel comprise a different type of material than the main body region of the channel.