# US 10,504,881 B2 · Stacked semiconductor die assemblies with support members and associated systems and methods > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,504,881 B2 - Document ID: US10504881B2 - Status: Granted - Kind: B2 - Application number: 15/229,651 - Filed: 2016-08-05 - Published: 2016-11-24 - Granted: 2019-12-10 - Earliest claimed: 2014-04-29 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Hong Wan Ng; Seng Kim Ye - Web page: https://patentgrep.com/patent/US10504881B2 ## CPC - H10W 90/00: Package configurations - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 46/00: Marks applied to devices, e.g. for alignment or identification - H10W 70/655: Fan-out layouts - H10W 70/656: Fan-in layouts - H10W 72/073: {of die-attach connectors} - H10W 72/07332: {Compression bonding, e.g. thermocompression bonding} - H10W 72/07337: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy} - H10W 72/07338: {hardening the adhesive by curing, e.g. thermosetting} - H10W 72/07354: {changes in dispositions} - H10W 72/075: {of bond wires} - H10W 72/347: {Dispositions of multiple die-attach connectors} - H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements} - H10W 72/59: Bond pads specially adapted therefor - H10W 72/884: {Die-attach connectors and bond wires} - H10W 72/932: {Plan-view shape, i.e. in top view} - H10W 72/9445: {Top-view layouts, e.g. mirror arrays} - H10W 72/951: {Materials of bond pads} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/20: Configurations of stacked chips - H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape - H10W 90/732: {between stacked chips} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Stacked semiconductor die assemblies with support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a plurality of support members also attached to the package substrate. The plurality of support members can include a first support member and a second support member disposed at opposite sides of the first semiconductor die, and a second semiconductor die can be coupled to the support members such that at least a portion of the second semiconductor die is over the first semiconductor die. ## Claims ### Claim 1 A method of manufacturing a semiconductor die assembly, the method comprising: attaching a first semiconductor die to a package substrate; positioning a first support member and a second support member on opposite sides of the first semiconductor die, wherein the first support member is substantially parallel to the second support member, and wherein the first support member is flush with a first border of a footprint of a second semiconductor die and the second support member is flush with a second border of the footprint of the second semiconductor die; positioning a third support member that is substantially perpendicular to the first and second support members, wherein the third support member is positioned wholly within the footprint of the second semiconductor die and set back from a closest border of the footprint of the second semiconductor die by a distance, and wherein the third support member is spaced apart from each of the first and second support members by a gap; attaching the second semiconductor die to the first, second, and third support members via a die-attach film such that (a) the first, second, and third support members carry the second semiconductor die above the first semiconductor die and (b) the first, second, and third support members, the second semiconductor die; and flowing an encapsulant into the cavity through the gap to at least partially provide mechanical support for the second semiconductor die. ### Claim 2 (depends on 1) The method of claim 1, further comprising: wirebonding first bond pads of the package substrate to corresponding bond pads of the first semiconductor die; and wirebonding second bond pads of the package substrate to corresponding bond pads of the second semiconductor die, wherein the first bond pads are within the footprint of the second semiconductor die. ### Claim 3 (depends on 1) The method of claim 1 wherein the die-attach film is a first die-attach film, and wherein attaching the first semiconductor die to the package substrate includes attaching the first semiconductor die to the package substrate with a second die-attach film. ### Claim 4 (depends on 1) The method of claim 1 wherein the die-attach film is a first die-attach film, and wherein positioning the first support member and the second support member includes: attaching the first support member to the package substrate with a second die-attach film; and attaching the second support member to the package substrate with a third die-attach film. ### Claim 5 (depends on 1) The method of claim 1 wherein the die-attach film does not attach the first semiconductor die to the second semiconductor die. ### Claim 6 (depends on 5) The method of claim 5, further comprising forming wirebonds that electrically couple the first semiconductor die with the package substrate, wherein a portion of the wirebonds projects into the die-attach film. ### Claim 7 A method of manufacturing a semiconductor die assembly, the method comprising: attaching a first semiconductor die to a package substrate; positioning a first support member and a second support member on opposite sides of the first semiconductor die, wherein the first support member is substantially parallel to the second support member, and wherein the first support member is flush with a first border of a footprint of a second semiconductor die and the second support member is flush with a second border of the footprint of the second semiconductor die, wherein positioning the first support member and the second support member includes— covering a semiconductor wafer with a die-attach material; cutting the semiconductor wafer to form elongate semiconductor members each having a portion of the die-attach material attached thereto; and attaching the elongate semiconductor members to the package substrate via the portion of the die-attach material attached to each of the elongate semiconductor members; positioning a third support member that is substantially perpendicular to the first and second support members, wherein the third support member is positioned wholly within the footprint of the second semiconductor die and set back from a closest border of the footprint of the second semiconductor die by a distance, and wherein the third support member is spaced apart from each of the first and second support members by a gap; attaching the second semiconductor die to the first, second, and third support members such that the first, second, and third support members carry the second semiconductor die above the first semiconductor die; forming wirebonds electrically coupling bond pads of the package substrate to corresponding bond pads of the second semiconductor die; and attaching a third semiconductor die to the second semiconductor die via an over-wire material, wherein a portion of the wirebonds extend into the over-wire material. ### Claim 8 (depends on 1) The method of claim 1, further comprising coupling first bond pads of the package substrate to corresponding second bond pads of the first semiconductor die with wirebonds, wherein the first bond pads are within the footprint of the second semiconductor die, and wherein attaching the second semiconductor die includes attaching the second semiconductor die to the first, second, and third support members via the die-attach film such that the wirebonds do not contact the die-attach film. ### Claim 9 (depends on 5) The method of claim 5 wherein the die-attach film has a uniform thickness. ### Claim 10 (depends on 1) The method of claim 1, further comprising: forming wirebonds electrically coupling bond pads of the package substrate to corresponding bond pads of the second semiconductor die; and attaching a third semiconductor die to the second semiconductor die via an over-wire material, wherein a portion of the wirebonds extend into the over-wire material. ### Claim 11 (depends on 10) The method of claim 10 wherein— the wirebonds are first wirebonds, the bond pads of the package substrate are first bond pads, the method further comprises forming second wirebonds electrically coupling second bond pads of the package substrate to corresponding bond pads of the first semiconductor die, and a portion of the second wirebonds projects into the die-attach film. ### Claim 12 (depends on 11) The method of claim 11 wherein the die-attach material has a uniform first thickness, and wherein the over-wire material has a uniform second thickness, greater than the first thickness. ### Claim 13 (depends on 7) The method of claim 7 wherein the first, second, and third support members, the second semiconductor die, and the package substrate together define a cavity beneath the second semiconductor die, and wherein the method further includes flowing an encapsulant into the cavity through the gap to at least partially provide mechanical support for the second semiconductor die.