# US 10,504,880 B2 · Method of forming semicondcutor device package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,504,880 B2 - Document ID: US10504880B2 - Status: Granted - Kind: B2 - Application number: 16/396,765 - Filed: 2019-04-29 - Published: 2019-08-15 - Granted: 2019-12-10 - Earliest claimed: 2017-07-03 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd. - Inventors: Po-Yao Lin; Cheng-Yi Hong; Feng-Cheng Hsu; Shuo-Mao Chen; Shin-Puu Jeng; Shu-Shen Yeh; Kuang-Chun Lee - Web page: https://patentgrep.com/patent/US10504880B2 ## CPC - H10W 90/00: Package configurations - H10P 72/74: {using temporarily an auxiliary support} - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/611: {for connecting multiple chips together} - H10W 70/685: comprising multiple insulating layers - H10W 74/01: Manufacture or treatment - H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 76/47: Solid or gel fillings - H10W 90/288: {characterised by arrangements for thermal management of the stacked chips} - H10P 72/7424: {used as a support during the manufacture of self-supporting substrates} - H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer} - H10W 40/253: {Semiconductors} - H10W 40/258: {Metallic materials (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence)} - H10W 40/259: {Ceramics or glasses (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence)} - H10W 72/877: {Bump connectors and die-attach connectors} - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A method of forming a semiconductor device package includes the following steps. A redistribution structure is formed on a carrier. A plurality of second semiconductor devices are disposed on the redistribution structure. At least one warpage adjusting component is disposed on at least one of the second semiconductor devices. A first semiconductor device is disposed on the redistribution structure. An encapsulating material is formed on the redistribution structure to encapsulate the first semiconductor device, the second semiconductor devices and the warpage adjusting component. The carrier is removed to reveal a bottom surface of the redistribution structure. A plurality of electrical terminals are formed on the bottom surface of the redistribution structure. ## Claims ### Claim 1 A method of forming a semiconductor device package comprising: forming a redistribution structure on a carrier; disposing a plurality of second semiconductor devices on the redistribution structure; disposing at least one warpage adjusting component on at least one of the second semiconductor devices; disposing a first semiconductor device on the redistribution structure; forming an encapsulating material on the redistribution structure to encapsulate the first semiconductor device, the second semiconductor devices and the warpage adjusting component; removing the carrier to reveal a bottom surface of the redistribution structure; and forming a plurality of electrical terminals on the bottom surface of the redistribution structure. ### Claim 2 (depends on 1) The method as claimed in claim 1, wherein a Young's modulus of the warpage adjusting component is greater than or equal to a Young's modulus of the encapsulating material, and a coefficient of thermal expansion (CTE) of the warpage adjusting component is smaller than a CTE of the encapsulating material. ### Claim 3 (depends on 1) The method as claimed in claim 1, wherein the first semiconductor device is a system on chip (SOC), each of the second semiconductor devices is a dynamic random access memory (DRAM) chip-scale package (CSP), and the second semiconductor devices surround the first semiconductor device. ### Claim 4 (depends on 1) The method as claimed in claim 1, wherein disposing the at least one warpage adjusting component on the at least one of the second semiconductor devices comprises: attaching the at least one warpage adjusting component to a back surface of the at least one of the second semiconductor devices, wherein the back surface faces away from the redistribution structure. ### Claim 5 (depends on 1) The method as claimed in claim 1, wherein the number of the at least one warpage adjusting component is plural, and the warpage adjusting components are disposed on at least a set of the second semiconductor devices respectively. ### Claim 6 (depends on 1) The method as claimed in claim 1, further comprising: forming an underfill to fill between the first semiconductor device and the redistribution structure and fill between the second semiconductor devices and redistribution structure before the encapsulating material is formed. ### Claim 7 (depends on 1) The method as claimed in claim 1, wherein the first semiconductor device and the plurality of second semiconductor devices are disposed on the redistribution structure through a plurality of connectors. ### Claim 8 (depends on 1) The method as claimed in claim 1, wherein a thickness of the first semiconductor device is substantially greater than a thickness of each of the plurality of second semiconductor devices, the encapsulating material reveals a back surface of the first semiconductor device and covers back surfaces of the plurality of second semiconductor devices. ### Claim 9 A method of forming a semiconductor device package comprising: forming a redistribution structure on a carrier; disposing a plurality of second semiconductor devices on the redistribution structure; disposing a first semiconductor device on the redistribution structure; forming an encapsulating material on the redistribution structure to encapsulate the first semiconductor device and the second semiconductor devices; disposing at least one warpage adjusting component over the encapsulating material and at least one of the second semiconductor devices; removing the carrier to reveal a bottom surface of the redistribution structure; and forming a plurality of electrical terminals on the bottom surface of the redistribution structure. ### Claim 10 (depends on 9) The method as claimed in claim 9, further comprising: performing a grinding process on the encapsulating material, such that a top surface of the encapsulating material is coplanar with the back surface of the first semiconductor device and the back surfaces of the second semiconductor devices. ### Claim 11 (depends on 9) The method as claimed in claim 9, wherein the at least one warpage adjusting component is in contact with a top surface of the encapsulating material, a back surface of the first semiconductor device and back surfaces of the second semiconductor devices. ### Claim 12 (depends on 9) The method as claimed in claim 9, wherein the at least one warpage adjusting frame is in a ring form, which is in contact with a top surface of the encapsulating material and back surfaces of the second semiconductor devices and reveals a back surface of the first semiconductor device. ### Claim 13 (depends on 9) The method as claimed in claim 9, wherein the material of the at least one warpage adjusting frame comprises stainless steel, copper, aluminum or wolfram. ### Claim 14 (depends on 9) The method as claimed in claim 9, wherein the first semiconductor device is a system on chip (SOC), each of the second semiconductor devices is a dynamic random access memory (DRAM) chip-scale package (CSP), and the second semiconductor devices surround the first semiconductor device. ### Claim 15 (depends on 9) The method as claimed in claim 9, wherein disposing the at least one warpage adjusting component over the encapsulating material and the at least one of the second semiconductor devices comprises: attaching the at least one warpage adjusting component to a top surface of the encapsulating material and the back surface of the at least one of the second semiconductor devices by an adhesive, wherein the back surface faces away from the redistribution structure. ### Claim 16 A method of forming a semiconductor device package comprising: forming a redistribution structure; disposing a plurality of second semiconductor devices on the redistribution structure; disposing at least one warpage adjusting component on at least one of the second semiconductor devices; disposing a first semiconductor device on the redistribution structure; and forming an encapsulating material on the redistribution structure to encapsulate the first semiconductor device, the second semiconductor devices and the warpage adjusting component. ### Claim 17 (depends on 16) The method as claimed in claim 16, wherein a Young's modulus of the warpage adjusting component is greater than or equal to a Young's modulus of the encapsulating material, and a coefficient of thermal expansion (CTE) of the warpage adjusting component is smaller than a CTE of the encapsulating material. ### Claim 18 (depends on 16) The method as claimed in claim 16, further comprising: forming a plurality of electrical terminals on a bottom surface of the redistribution structure. ### Claim 19 (depends on 16) The method as claimed in claim 16, wherein disposing the at least one warpage adjusting component on the at least one of the second semiconductor devices comprises: attaching the at least one warpage adjusting component to a back surface of the at least one of the second semiconductor devices, wherein the back surface faces away from the redistribution structure. ### Claim 20 (depends on 16) The method as claimed in claim 16, wherein the number of the at least one warpage adjusting component is plural, and the warpage adjusting components are disposed on at least a set of the second semiconductor devices respectively.