# US 10,504,873 B1 · 3DIC structure with protective structure and method of fabricating the same and package

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,504,873 B1
- Document ID: US10504873B1
- Status: Granted
- Kind: B1
- Application number: 16/016,670
- Filed: 2018-06-25
- Published: 2019-12-26
- Granted: 2019-12-10
- Earliest claimed: 2018-06-25
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Hsien-Wei Chen; Ching-Jung Yang; Ming-Fa Chen
- Web page: https://patentgrep.com/patent/US10504873B1

## CPC

- H10W 90/00: Package configurations
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/0249: {wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture}
- H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating}
- H10W 20/062: {by smoothing of conductive parts, e.g. by planarisation}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/43: Layouts of interconnections
- H10W 72/90: Bond pads, in general
- H10W 74/01: Manufacture or treatment
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/68: Shapes or dispositions thereof
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/354: {comprising polymers}
- H10W 72/874: {On different surfaces}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 80/334: {Thermocompression bonding}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Provided is a three-dimensional integrated circuit (3DIC) structure including a die stack structure, a metal circuit structure, and a protective structure. The die stack structure includes a first die and a second die face-to-face bonded together. The metal circuit structure is disposed over a back side of the second die. The protective structure is disposed within the back side of the second die and separates one of a plurality of through-substrate vias (TSVs) of the second die from the metal circuit structure.

## Claims

### Claim 1

A three-dimensional integrated circuit (3DIC) structure, comprising:
a die stack structure comprising a first die having a front side and a back side and a second die having a front side and a back side, the front side of the first die bonded to the front side of the second die, the second die including a plurality of through-substrate vias (TSVs);
a metal circuit structure disposed over the back side of the second die; and
a first protective structure disposed within the back side of the second die and separating and electrically isolating one of the plurality of TSVs of the second die from the metal circuit structure.

### Claim 2 (depends on 1)

The 3DIC structure of claim 1, wherein a top surface of the first protective structure and the back side of the second die are substantially coplanar.

### Claim 3 (depends on 1)

The 3DIC structure of claim 1, wherein the first protective structure comprises a conformal layer.

### Claim 4 (depends on 1)

The 3DIC structure of claim 1, wherein the first protective structure comprises a composite structure comprising a conformal layer and a filling layer disposed over the conformal layer, and the conformal layer and the filling layer are formed of different materials.

### Claim 5 (depends on 1)

The 3DIC structure of claim 1, wherein the die stack structure further comprises a hybrid bonding structure disposed between the first die and the second die.

### Claim 6 (depends on 5)

The 3DIC structure of claim 5, further comprising a second protective structure disposed within the back side of the second die, wherein the first protective structure is in direct contact with one of the plurality of TSVs and the second protective structure is spaced apart from the plurality of TSVs.

### Claim 7 (depends on 5)

The 3DIC structure of claim 5, wherein the first protective structure extends from the back side of the second die into the hybrid bonding structure.

### Claim 8 (depends on 1)

The 3DIC structure of claim 1, wherein another of the plurality of TSVs is electrically connected to the metal circuit structure, and a top surface of the one of the plurality of TSVs of the second die is lower than a top surface of the another of the plurality of TSVs of the second die.

### Claim 9 (depends on 1)

The 3DIC structure of claim 1, further comprising:
a dielectric layer, laterally encapsulating the second die; and
a through-dielectric via (TDV), disposed in the dielectric layer and electrically connected to the first die and the metal circuit structure.

### Claim 10 (depends on 9)

The 3DIC structure of claim 9, wherein a top surface of the dielectric layer, a top surface of TDV, the top surface of the first protective structure and the back side of the second die are substantially coplanar.

### Claim 11 (depends on 1)

The 3DIC structure of claim 1, wherein the die stack structure comprises a chip-on-wafer (CoW) structure, a chip-on-chip structure, a die-on-die structure or a combination thereof.

### Claim 12

A method of manufacturing a 3DIC structure, comprising:
forming a die stack structure comprising a first die and a second die face-to-face bonded together;
performing a first planarization process to expose a plurality of through-substrate vias (TSVs) of the second die at a back side of the second die, wherein the back side of the second die has a first recess that extends into one of the plurality of TSVs of the second die;
filling a protective structure in the first recess with a conformal layer; and
forming a metal circuit structure over the back side of the second die to electrically connected to the die stack structure through another of the plurality of TSVs, wherein the protective structure electrically isolates the one of the plurality of TSVs of the second die from the metal circuit structure.

### Claim 13 (depends on 12)

The method of claim 12, wherein the filling the protective structure in the first recess comprises:
performing an atomic layer deposition (ALD) process to form the conformal layer over the back side of the second die, wherein the conformal layer completely covers a surface of the first recess;
performing a chemical vapor deposition (CVD) process to forming a filling layer over the conformal layer; and
performing a second planarization process to expose another of the plurality of TSVs of the second die.

### Claim 14 (depends on 12)

The method of claim 12, wherein the forming the die stack structure comprises:
providing the first die and the second die; and
forming a hybrid bonding structure between the first die and the second die to bond the first die and the second die.

### Claim 15 (depends on 14)

The method of claim 14, wherein the back side of the second die includes a second recess after performing the first planarization process, the first and second recesses extend along a direction from the back side of the second die toward the hybrid bonding structure, and the second recess is spaced apart from the plurality of TSVs of the second die.

### Claim 16 (depends on 14)

The method of claim 14, wherein the first recess extends from the back side of the second die into the hybrid bonding structure after performing the first planarization process.

### Claim 17 (depends on 12)

The method of claim 12, wherein a top surface of the one of the plurality of TSVs of the second die is lower than a top surface of the another of the plurality of TSVs of the second die after performing the first planarization process.

### Claim 18 (depends on 12)

The method of claim 12, wherein a top surface of the protective structure and the back side of the second die are substantially coplanar after performing the second planarization process.

### Claim 19

A package, comprising:
a 3DIC structure comprising a die stack structure, a metal circuit structure, and a protective structure between the die stack structure and the metal circuit structure, wherein the metal circuit structure is electrically connected to the die stack structure through one of a plurality of through-substrate vias (TSVs) of the die stack structure, and the protective structure separates and electrically isolates another of the plurality of TSVs of the die stack structure from the metal circuit structure;
an insulating encapsulation, laterally encapsulating the 3DIC structure;
a redistribution layer (RDL) structure, disposed over the 3DIC structure and the insulating encapsulation; and
a plurality of connectors, disposed over and electrically connected to the 3DIC structure through the RDL structure.

### Claim 20 (depends on 19)

The package of claim 19, wherein the die stack structure comprises a first die and a plurality of second dies arranged in parallel over the first die.