# US 10,504,865 B2 · Package structure and method of manufacturing the same

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- Number: US 10,504,865 B2
- Document ID: US10504865B2
- Status: Granted
- Kind: B2
- Application number: 15/717,974
- Filed: 2017-09-28
- Published: 2019-03-28
- Granted: 2019-12-10
- Earliest claimed: 2017-09-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Ming-Kai Liu; Han-Ping Pu; Ting-Chu Ko; Yung-Ping Chiang; Chang-Wen Huang; Yu-Sheng Hsieh
- Web page: https://patentgrep.com/patent/US10504865B2

## CPC

- H10W 90/00: Package configurations
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/635: {Through-vias}
- H10W 70/685: comprising multiple insulating layers
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/654: Top-view layouts
- H10W 70/655: Fan-out layouts
- H10W 72/073: {of die-attach connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/874: {On different surfaces}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/9413: {on encapsulations}
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Provided is a package structure includes a die having a first connector, a RDL structure disposed on the die, and a second connector. The RDL structure includes at least one elongated via located on and connected to the first connector. The second connector is disposed on and connected to the RDL structure.

## Claims

### Claim 1

A package structure, comprising:
a die having a first connector;
an encapsulant, laterally encapsulating sidewalls of the die;
a RDL structure disposed on the die and the encapsulant, the RDL structure comprises:
a dielectric layer on top surfaces of the die and the encapsulant; and
a redistribution layer, penetrating through the dielectric layer to connect to the die; comprising:
at least one elongated via located on and connected to the first connector, wherein the at least one elongated via is embedded in the dielectric layer, and comprises a first seed layer and a first conductive layer on the first seed layer; and
at least one trace, extending on and in contact with top surfaces of the at least one elongated via and the dielectric layer, the at least one trace comprises a second seed layer and a second conductive layer on the second seed layer, wherein the second seed layer is separated from the first seed layer by the first conductive layer therebetween; and
a second connector disposed on and connected to the RDL structure,
wherein the elongated via comprises an elongated bottom surface contacting with and extending along a top surface of the first connector, the elongated bottom surface comprises a length extending along a first direction and a width extending along a second direction perpendicular to the first direction,
wherein the length of the elongated bottom surface is larger than the width of the elongated bottom surface.

### Claim 2 (depends on 1)

The package structure of claim 1, wherein the at least one elongated via comprises a first elongated via and a second elongated via arranged in parallel.

### Claim 3 (depends on 2)

The package structure of claim 2, wherein the at least one trace comprises a first trace and a second trace arranged in parallel and connected to the first elongated via and the second elongated via respectively.

### Claim 4 (depends on 1)

The package structure of claim 1, wherein the at least one elongated via comprises a first elongated via and a second elongated via landed on a same first connector of the die.

### Claim 5 (depends on 1)

The package structure of claim 1, wherein the elongated via comprises a sidewall, and a base angle of the elongated via defined by the sidewall and the elongated bottom surface is equal to or less than 90°.

### Claim 6 (depends on 1)

The package structure of claim 1, wherein the top surface of the at least one elongated via is opposite to the elongated bottom surface, and wherein the elongated bottom surface has an area larger than an area of the top surface.

### Claim 7 (depends on 6)

The package structure of claim 6, wherein a shape of the elongated via is configured as a truncated cone.

### Claim 8 (depends on 6)

The package structure of claim 6, wherein the first seed layer has an extension protruding from a sidewall of the first conductive layer.

### Claim 9

A package structure, comprising:
a die having a first connector;
an encapsulant, laterally encapsulating sidewalls of the die;
a RDL structure disposed over the die and the encapsulant, wherein the RDL structure comprises:
a dielectric layer on top surfaces of the die and the encapsulant; and
a via embedded in the dielectric layer and located on the first connector, wherein an area of a bottom surface of the via is larger than an area of a top surface of the via, and the bottom surface is in contact with and electrically connected to the first connector, wherein the via comprises a first seed layer and a first conductive layer on the first seed layer, and a portion of a top surface of the first seed layer is in contact with the dielectric layer; and
a second connector disposed on and connected to the RDL structure.

### Claim 10 (depends on 9)

The package structure of claim 9, wherein the via is tapered toward the second connector.

### Claim 11 (depends on 9)

The package structure of claim 9, wherein the RDL structure further comprises a trace extending on the top surface of the via and a top surface of the dielectric layer, the trace comprises a second seed layer and a second conductive layer on the second seed layer, wherein the second conductive layer is separated from the first conductive layer by the second seed layer therebetween.

### Claim 12 (depends on 9)

The package structure of claim 9, wherein the first seed layer has the bottom surface and the first conductive layer has the top surface.

### Claim 13 (depends on 9)

The package structure of claim 9, wherein the first seed layer has an extension protruding from a sidewall of the first conductive layer, and the portion of the top surface of the first seed layer is a top surface of the extension.

### Claim 14 (depends on 9)

The package structure of claim 9, wherein a top surface of the first seed layer and a top surface of the first conductive layer have substantially identical shapes.

### Claim 15 (depends on 9)

The package structure of claim 9, wherein a top surface of the first seed layer and a top surface of the first conductive layer have different shapes.

### Claim 16

A method of manufacturing a package structure, comprising:
forming an encapsulant aside a die having a first connector, so as to laterally encapsulating sidewalls of the die;
forming a RDL structure on the die and the encapsulant, wherein RDL structure comprises a dielectric layer on top surfaces of the die and the encapsulant; and a redistribution layer penetrating through the dielectric layer to connect to the die, the forming the RDL structure comprising:
forming at least one elongated via located on and connected to the first connector, wherein the at least one elongated via comprises a first seed layer and a first conductive layer on the first seed layer;
forming the dielectric layer, such that the at least one elongated via is embedded in the dielectric layer; and
forming at least one trace extending on and in contact with top surfaces of the at least one elongated via and the dielectric layer, the at least one trace comprises a second seed layer and a second conductive layer on the second seed layer, wherein the second seed layer is separated from the first seed layer by the first conductive layer therebetween; and
forming a second connector over and connected to the RDL structure,
wherein the elongated via comprises an elongated bottom surface contacting and extending along a top surface of the first connector, the elongated bottom surface comprises a length extending along a first direction and a width extending along a second direction perpendicular to the first direction,
wherein the length of the elongated bottom surface is larger than the width of the elongated bottom surface.

### Claim 17 (depends on 16)

The method of claim 16, further comprises performing a treatment process on the first conductive layer before forming the dielectric layer, such that the top surface of the at least one elongated via is smaller than the elongated bottom surface of the at least one elongated via, wherein the treatment process comprises an anisotropic etch process.

### Claim 18 (depends on 17)

The method of claim 17, wherein the anisotropic process comprises a wet etch process.

### Claim 19 (depends on 17)

The method of claim 17, wherein the treatment process is performed so that the at least one elongated via is tapered away from the first connector.

### Claim 20 (depends on 16)

The method of claim 16, wherein forming the at least one elongated via comprises:
forming a first seed material layer on the die and the encapsulant;
forming a patterned mask layer on the first seed material layer;
forming the first conductive layer on the first seed material layer exposed by the patterned mask layer;
removing the patterned mask layer; and
removing a portion of the first seed material layer not coved by the first conductive layer, so as to form the first seed layer, and the first seed layer and the first conductive layer constitute the at least one elongated via.