# US 10,504,863 B2 · Variable ball height on ball grid array packages by solder paste transfer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,504,863 B2 - Document ID: US10504863B2 - Status: Granted - Kind: B2 - Application number: 16/198,429 - Filed: 2018-11-21 - Published: 2019-03-28 - Granted: 2019-12-10 - Earliest claimed: 2016-03-28 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Eric J. Li; Jimin Yao; Shawna M. Liff - Web page: https://patentgrep.com/patent/US10504863B2 ## CPC - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 70/098: {Applying pastes or inks, e.g. screen printing (H10W70/095 takes precedence)} - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/68: Shapes or dispositions thereof - H10W 72/01204: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates} - H10W 72/227: {Multiple bumps having different sizes} - H10W 72/248: {Top-view layouts, e.g. mirror arrays} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract BGA packages with a spatially varied ball height, molds and techniques to form such packages. A template or mold with cavities may be pre-fabricated to hold solder paste material applied to the mold, for example with a solder paste printing process. The depth and/or diameter of the cavities may be predetermined as a function of spatial position within the mold working surface area. Mold cavity dimensions may be specified corresponding to package position to account for one or more pre-existing or expected spatial variations in the package, such as a package-level warpage measurement. Any number of different ball heights may be provided. The molds may be employed in a standardize process that need not be modified with each change in the mold. ## Claims ### Claim 1 An integrated circuit (IC) package, comprising: one or more integrated circuit chips coupled to a chip-side of a package substrate; and a plurality of solder features over a land-side of the package substrate, opposite the chip-side, wherein: each of the solder features is within one of a plurality of openings in a solder resist, the plurality of openings comprising openings of varying area associated with different opening diameters, and each of the solder features have a lateral width that is a function of the different opening diameters; the solder features include a first solder feature having a first height and a second solder feature having a second height, the second height exceeding the first height by more than 25% of the first height; and variation in the solder feature heights is independent of the different opening diameters. ### Claim 2 (depends on 1) The IC package of claim 1, wherein the plurality of solder features comprise a ball grid array surrounding one or more land-side components coupled to the land-side of the package substrate. ### Claim 3 (depends on 1) The IC package of claim 1, wherein the the first solder feature is within an interior portion of the land-side of the package substrate; and the first solder features is surrounded by a perimeter of solder features having at least the second height. ### Claim 4 (depends on 1) The IC package of claim 1, wherein: the first solder height is no more than 240 μm; and the second solder height is at least 300 μm. ### Claim 5 (depends on 1) The IC package of claim 1, wherein the solder features comprise Sn, Ag, and Cu. ### Claim 6 (depends on 1) The IC package of claim 1, wherein: each of the first and second ones of the solder features has a spherical free surface over at least a portion of their height; the solder features comprise a SnAgCu alloy; and the second one of the solder features is more proximal a perimeter edge of the package substrate than the first one of the solder features. ### Claim 7 (depends on 1) The IC package of claim 1, wherein: the plurality of solder features further comprises a third solder feature having a third height, the third height exceeding the second height by more than 10% of the second height; and the second solder features is more proximal a perimeter edge of the package substrate than the first solder feature, and the third solder features is more proximal the perimeter edge of the package substrate than the second solder feature. ### Claim 8 (depends on 1) The IC package of claim 1, wherein: the plurality of solder features further comprises a third solder feature having a third height, the third height exceeding the second height by more than 10% of the second height; the second solder feature is more proximal a perimeter edge of the package substrate than the first solder feature, and the third solder features is more proximal a perimeter corner of the package substrate than the second solder feature. ### Claim 9 (depends on 1) The IC package of claim 1, wherein: a portion of the first solder feature is on a first BGA land exposed within a first opening in the solder resist; a portion of the second solder feature is on a second BGA land exposed within a second opening in the solder resist; and a diameter of the second opening is smaller than a diameter of the first opening. ### Claim 10 A computer system, comprising: a memory; and a processor coupled to the memory, wherein the processor is coupled to a chip-side of a package substrate that has a land-side opposite the chip-side; wherein a plurality of solder features contact the land-side, each of the solder features within one of a plurality of openings in a solder resist, wherein: the plurality of openings comprising openings of varying area associated with different opening diameters, and each of the solder features have a lateral width that is a function of the different opening diameters; the solder features include a first solder feature having a first height, and a second solder feature having a second height, the second height exceeding the first height by more than 25% of the first height; and the variation in the solder feature height is independent of the different opening diameters. ### Claim 11 (depends on 10) The computer system of claim 10, wherein the package substrate is a flip chip ball grid array (FCBGA) package substrate. ### Claim 12 (depends on 10) The computer system of claim 10, wherein the solder features comprise Sn, Ag, and Cu. ### Claim 13 (depends on 10) The computer system of claim 10, wherein the first solder height is no more than 240 μm and the second solder height is at least 260 μm. ### Claim 14 (depends on 10) The computer system of claim 10, further comprising: a plurality of land-side components within an interior portion of the land-side of the package substrate.