# US 10,504,862 B2 · Redistribution metal and under bump metal interconnect structures and method

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- Number: US 10,504,862 B2
- Document ID: US10504862B2
- Status: Granted
- Kind: B2
- Application number: 15/792,922
- Filed: 2017-10-25
- Published: 2019-04-25
- Granted: 2019-12-10
- Earliest claimed: 2017-10-25
- Assignees: Avago Technologies International Sales Pte. Limited
- Applicants: Avago Technologies International Sales Pte. Limited
- Inventors: Sam Ziqun Zhao; Liming Tsau; Edward Law; Andy Brotman
- Web page: https://patentgrep.com/patent/US10504862B2

## CPC

- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/66: Conductive materials thereof
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/232: {Plan-view shape, i.e. in top view}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/251: {Materials}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/9223: {with redistribution layers [RDL]}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9232: {with additional elements interposed between layers}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit die includes a metal layer, a first passivation layer disposed above the metal layer, an aluminum containing redistribution layer disposed above the first passivation layer, an under bump metallization layer, and a redistribution layer plug. The redistribution layer plug is coupled to the metal layer and disposed in a via in the first passivation layer. The under bump metallization layer is coupled to the aluminum containing redistribution layer above the first passivation layer at a distance from the redistribution layer plug.

## Claims

### Claim 1

An integrated circuit die, comprising:
a metal layer;
a first passivation layer disposed above the metal layer;
a redistribution layer disposed above the first passivation layer, wherein the redistribution layer is planar with a bottom surface in direct contact with the first passivation layer; and
a redistribution layer plug disposed in a via through the first passivation layer, wherein a top surface of the redistribution layer plug is substantially in-plane with the bottom surface of the redistribution layer, and a bottom surface of the redistribution layer plug is substantially in-plane with the metal layer, wherein material of the redistribution layer is not within the via; and
an under bump metallization layer coupled to the redistribution layer above the first passivation layer at a lateral distance from the redistribution layer plug.

### Claim 2 (depends on 1)

The integrated circuit die of claim 1, wherein the redistribution layer plug comprises tungsten, titanium, titanium nitride, titanium-tungsten, or nickel silicide.

### Claim 3 (depends on 2)

The integrated circuit die of claim 2, wherein the under bump metallization layer is connected to the metal layer at a location directly below a bump structure attached to the under bump metallization layer.

### Claim 4 (depends on 1)

The integrated circuit die of claim 1, wherein the redistribution layer plug comprises copper.

### Claim 5 (depends on 4)

The integrated circuit die of claim 4, wherein the top surface comprises tungsten, titanium, or tantalum.

### Claim 6 (depends on 1)

The integrated circuit die of claim 1, wherein the under bump metallization layer is coupled to the redistribution layer through a polyimide layer, the redistribution layer comprising, copper, aluminum, gold or mixtures thereof.

### Claim 7

An integrated circuit die, comprising:
a metal layer;
a first passivation layer disposed above the metal layer;
a conductive layer disposed above the first passivation layer;
a polyimide layer disposed above the conductive layer; and
an under bump metallization layer extended to the metal layer through the polyimide layer, the conductive layer, and the first passivation layer, wherein the under bump metallization layer directly contacts the metal layer and the conductive layer.

### Claim 8 (depends on 7)

The integrated circuit die of claim 7, wherein the under bump metallization layer is provided through a first hole in the polyimide layer, a second hole in the conductive layer, and a third hole in the first passivation layer, the first hole being larger than the second hole and the second hole at a bottom being substantially the same size as the third hole at a top.

### Claim 9 (depends on 7)

The integrated circuit die of claim 7, wherein the under bump metallization layer is provided through a first hole in the polyimide layer, a second hole in the conductive layer, and a third hole in the first passivation layer, the first hole being larger than the second hole and the second hold being larger than the third hole.

### Claim 10 (depends on 7)

The integrated circuit die of claim 7, further comprising a second passivation layer above the first passivation layer and at least partially above the conductive layer.

### Claim 11 (depends on 7)

The integrated circuit die of claim 7 wherein the under bump metallization layer comprises copper.

### Claim 12

An integrated circuit die, comprising:
a metal layer;
a barrier layer above the metal layer;
a first passivation layer disposed above the barrier layer;
a redistribution layer disposed above the first passivation layer, wherein the redistribution layer does not contact the metal layer; and
an under bump metallization layer plug coupled to the metal layer and disposed in a via that is provided through the first passivation layer, the redistribution layer, and the barrier layer, wherein a top surface of the redistribution layer plug is disposed above a top surface of the redistribution layer.

### Claim 13 (depends on 12)

The integrated circuit die of claim 12, further comprising:
an under bump metallization layer coupled to the redistribution layer above the first passivation layer at a distance from the redistribution layer plug, wherein the under bump metallization layer comprises a material, the material being the same material as the under bump metallization layer plug.

### Claim 14 (depends on 12)

The integrated circuit die of claim 12, wherein the under bump metallization layer is connected to the metal layer without aluminum in the under bump metallization layer plug.

### Claim 15 (depends on 13)

The integrated circuit die of claim 13, wherein the under bump metallization layer plug comprises copper.

### Claim 16 (depends on 13)

The integrated circuit die of claim 13, further comprising:
a polyimide layer disposed above the redistribution layer, wherein the top surface of the under bump metallization layer plug extends above the polyimide layer and the redistribution layer comprises aluminum.

### Claim 17

An integrated circuit die, comprising:
a metal layer;
a first passivation layer disposed above the metal layer;
a first polyimide layer disposed above the first a passivation layer; and
an under bump metallization layer coupled to the metal layer through the first polyimide layer, wherein the under bump metallization layer comprises at least one conductor extending across a top surface of the first polyimide layer and away from an area for a solder bump or pillar for the integrated circuit die, wherein the under bump metallization layer is directly connected between the solder bump or pillar and the metal layer.

### Claim 18 (depends on 17)

The integrated circuit die of claim 17, further comprising a second polyimide layer having a top surface disposed directly above the under bump metallization layer and the conductor.

### Claim 19 (depends on 17)

The integrated circuit die of claim 17, wherein the under bump metallization layer and the conductor comprise copper.

### Claim 20 (depends on 17)

The integrated circuit die of claim 17, wherein the conductor is not covered by a dielectric.