# US 10,504,858 B2 · Package structure and method of fabricating the same

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- Number: US 10,504,858 B2
- Document ID: US10504858B2
- Status: Granted
- Kind: B2
- Application number: 15/964,091
- Filed: 2018-04-27
- Published: 2019-10-31
- Granted: 2019-12-10
- Earliest claimed: 2018-04-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Meng-Tse Chen; Ching-Hua Hsieh; Chung-Shi Liu; Chih-Wei Lin; Hao-Cheng Hou; Jung-Wei Cheng
- Web page: https://patentgrep.com/patent/US10504858B2

## CPC

- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/635: {Through-vias}
- H10W 74/014: {using batch processing}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/0198: {batch processes}
- H10W 72/073: {of die-attach connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/874: {On different surfaces}
- H10W 72/9413: {on encapsulations}
- H10W 90/722: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A package structure including a semiconductor die, a warpage control layer, an insulating encapsulant and a redistribution layer is provided. The semiconductor die has an active surface and a backside surface opposite to the active surface. The warpage control layer is disposed on the backside surface of the semiconductor die, wherein the warpage control layer comprises a material having a Young's Modulus of 100 GPa or more. The insulating encapsulant is encapsulating the semiconductor die and the warpage control layer. The redistribution layer is located on the insulating encapsulant and over the active surface of the semiconductor die.

## Claims

### Claim 1

A method of fabricating a package structure, comprising:
providing a semiconductor die, the semiconductor die has an active surface and a backside surface opposite to the active surface;
forming a warpage control layer on the backside surface of the semiconductor die, wherein the warpage control layer is formed of a material having a Young's Modulus of 100 GPa or more;
bonding the semiconductor die and the warpage control layer onto a carrier;
forming a plurality of through insulator vias on the carrier, wherein the plurality of through insulator vias is surrounding the semiconductor die;
forming an insulating encapsulant on the carrier after forming the plurality of through insulator vias to encapsulate the semiconductor die, the warpage control layer and the plurality of through insulator vias;
forming a redistribution layer on the insulating encapsulant, wherein the redistribution layer is electrically connected to the semiconductor die; and
de-bonding the carrier.

### Claim 2 (depends on 1)

The method of fabricating the package structure according to claim 1, wherein the warpage control layer is formed of a material selected from the group consisting of silicon nitride, aluminum nitride, tungsten carbide, boron carbide, silicon carbide, titanium carbide, graphene, diamond-like carbon (DLC), silicon oxide formed by low temperature plasma-enhanced chemical vapor deposition, and aluminum oxide.

### Claim 3 (depends on 1)

The method of fabricating the package structure according to claim 1, wherein the warpage control layer is formed of silicon nitride.

### Claim 4 (depends on 1)

The method of fabricating the package structure according to claim 1, wherein the warpage control layer is formed with a thickness in a range of 5 μm to 200 μm.

### Claim 5 (depends on 1)

The method of fabricating the package structure according to claim 1, further comprising:
forming a plurality of conductive terminals on the redistribution layer, wherein the plurality of conductive terminals is electrically connected to the semiconductor die through the redistribution layer.

### Claim 6 (depends on 1)

The method of fabricating the package structure according to claim 1, wherein the semiconductor die and the warpage control layer are bonded onto the carrier through a die attach film.

### Claim 7 (depends on 1)

The method of fabricating the package structure according to claim 1, further comprising:
forming a plurality of conductive balls on the plurality of through insulator vias after de-bonding the carrier.

### Claim 8

A method of fabricating a package structure, comprising:
providing a semiconductor die, the semiconductor die has an active surface and a backside surface opposite to the active surface;
forming a warpage control layer on the backside surface of the semiconductor die by plasma-enhanced chemical vapor deposition, wherein the plasma enhanced chemical vapor deposition is performed at temperatures below 200° C.;
bonding the semiconductor die and the warpage control layer onto a carrier;
forming a plurality of through insulator vias on the carrier to surround the semiconductor die and the warpage control layer;
forming an insulating encapsulant on the carrier to encapsulate the semiconductor die, the warpage control layer and the plurality of through insulator vias, wherein the insulating encapsulant has a first surface and a second surface opposite to the first surface;
forming a redistribution layer on the first surface of the insulating encapsulant, wherein the redistribution layer is electrically connected to the semiconductor die;
de-bonding the carrier; and
forming a plurality of conductive balls on the second surface of the insulating encapsulant.

### Claim 9 (depends on 8)

The method of fabricating the package structure according to claim 8, wherein the warpage control layer is formed of a material having a Young's Modulus of 100 GPa or more.

### Claim 10 (depends on 8)

The method of fabricating the package structure according to claim 8, wherein the warpage control layer is formed of a material selected from the group consisting of silicon nitride, aluminum nitride, tungsten carbide, boron carbide, silicon carbide, titanium carbide, graphene, diamond-like carbon (DLC), silicon oxide and aluminum oxide.

### Claim 11 (depends on 8)

The method of fabricating the package structure according to claim 8, wherein the warpage control layer is formed of silicon nitride.

### Claim 12 (depends on 8)

The method of fabricating the package structure according to claim 8, wherein the warpage control layer is formed with a thickness in a range of 5 μm to 200 μm.

### Claim 13 (depends on 8)

The method of fabricating the package structure according to claim 8, further comprising:
forming a plurality of conductive terminals on the redistribution layer, wherein the plurality of conductive terminals is electrically connected to the semiconductor die through the redistribution layer.

### Claim 14 (depends on 8)

The method of fabricating the package structure according to claim 8, wherein the semiconductor die and the warpage control layer are bonded onto the carrier through a die attach film.

### Claim 15

A method of fabricating a package structure, comprising:
providing a semiconductor die having a warpage control layer formed thereon, wherein the semiconductor die comprises a semiconductor substrate located at a backside of the semiconductor die, and a plurality of conductive posts located at an active surface opposite to the backside of the semiconductor die, and the warpage control layer is attached to the backside of the semiconductor die on the semiconductor substrate, and formed with a material having a Young's Modulus of 100 GPa or more;
bonding the semiconductor die onto a carrier through the warpage control layer; and
forming a plurality of through insulator vias on the carrier, wherein the plurality of through insulator vias is surrounding the semiconductor die;
forming an insulating encapsulant on the carrier after forming the plurality of through insulator vias to encapsulate the semiconductor die, the warpage control layer and the plurality of through insulator vias.

### Claim 16 (depends on 15)

The method of fabricating the package structure according to claim 15, further comprising:
forming a redistribution layer on the insulating encapsulant, wherein the redistribution layer is electrically connected to the semiconductor die; and
de-bonding the carrier.

### Claim 17 (depends on 16)

The method of fabricating the package structure according to claim 16, further comprising:
forming a plurality of conductive terminals on the redistribution layer, wherein the plurality of conductive terminals is electrically connected to the semiconductor die through the redistribution layer.

### Claim 18 (depends on 16)

The method of fabricating the package structure according to claim 16, further comprising:
forming a plurality of conductive balls on the plurality of through insulator vias after de-bonding the carrier.

### Claim 19 (depends on 15)

The method of fabricating the package structure according to claim 15, wherein the semiconductor die and the warpage control layer are bonded onto the carrier through a die attach film.

### Claim 20 (depends on 15)

The method of fabricating the package structure according to claim 15, wherein after bonding the semiconductor die onto the carrier, the warpage control layer is sandwiched in between the semiconductor substrate and the carrier.