# US 10,504,856 B2 · Scheme for connector site spacing and resulting structures

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,504,856 B2
- Document ID: US10504856B2
- Status: Granted
- Kind: B2
- Application number: 15/339,257
- Filed: 2016-10-31
- Published: 2017-02-16
- Granted: 2019-12-10
- Earliest claimed: 2012-05-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Yu-Feng Chen; Yen-Liang Lin; Tin-Hao Kuo; Sheng-Yu Wu; Chen-Shien Chen
- Web page: https://patentgrep.com/patent/US10504856B2

## CPC

- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 20/01: {Manufacture or treatment}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01255: {by using masks}
- H10W 72/019: {of bond pads}
- H10W 72/01953: {by etching}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/921: {Structures or relative sizes of bond pads}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 μm. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 μm. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 μm. In another embodiment the underbump metallization has a first dimension that is less than a dimension of the contact pad and a second dimension that is greater than a dimension of the contact pad.

## Claims

### Claim 1

A semiconductor device comprising: a first contact pad over a substrate, the first contact pad having a first symmetrical perimeter; and a first underbump metallization over and in physical contact with the first contact pad, wherein the first contact pad is located between the substrate and the first underbump metallization, the first underbump metallization having an elongated perimeter, the elongated perimeter having a first line of symmetry and a second line of symmetry, the elongated perimeter having a first width along the first line of symmetry and a second width along the second line of symmetry, the second width being different from the first width, the second line of symmetry being perpendicular to the first line of symmetry in a plan view, the elongated perimeter being located within the bounds of the first symmetrical perimeter along the first line of symmetry, the elongated perimeter extending outside the bounds of the first symmetrical perimeter along the second line of symmetry.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising:
a second contact pad over the substrate, the second contact pad having a second symmetrical perimeter; and
a second underbump metallization in physical contact with the second contact pad, the second underbump metallization having a perimeter being directly over the second symmetrical perimeter at least once in a top down view.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, further comprising:
a first external contact in connection with the first underbump metallization; and
a second external contact in connection with the second underbump metallization.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein a pitch between the first external contact and the second external contact is about 80 μm.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, further comprising:
a first redistribution line located between the first external contact and the second external contact; and
a second redistribution line located between the first external contact and the second external contact.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the first redistribution line has a width of between about 2 μm and about 14.5 μm.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the elongated perimeter is a rectangular perimeter.

### Claim 8

A semiconductor device comprising:
a first contact pad, the first contact pad having a first shape;
a first passivation layer at least partially overlying the first contact pad;
a first opening through the first passivation layer, the first opening having a second shape different from the first shape, the second shape of the first opening staying within the bounds of the first shape of the first contact pad in a top down view;
a second passivation layer at least partially overlying the first contact pad;
a second opening through the second passivation layer, the second opening having the second shape, the second shape of the second opening staying within the bounds of the first shape of the first contact pad in the top down view; and
an underbump metallization extending through the first opening and the second opening to make contact with the first contact pad, the underbump metallization having the second shape, the second shape of the underbump metallization having a first portion and a second portion, the first portion and the second portion having different widths, the first portion being located within the bounds of the first shape of the first contact pad in the top down view, the second portion extending outside of the bounds of the first shape of the first contact pad in the top down view.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the second opening has a first dimension in a first direction, the first opening has a second dimension greater than the first dimension in the first direction, and the underbump metallization has a third dimension greater than the second dimension in the first direction.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, wherein the first contact pad has a first dimension in a first direction and a second dimension in a second direction perpendicular to the first direction, wherein the first dimension is equal to the second dimension.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, wherein the first contact pad has a first dimension in a first direction and a second dimension in a second direction perpendicular to the first direction, wherein the first dimension is different from the second dimension.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, wherein the underbump metallization comprises a rectangular shape.

### Claim 13 (depends on 8)

The semiconductor device of claim 8, wherein the underbump metallization comprises an elliptic shape.

### Claim 14 (depends on 8)

The semiconductor device of claim 8, wherein the underbump metallization comprises an oval shape.

### Claim 15

A semiconductor device comprising:
a first contact pad over a substrate, the first contact pad having a first perimeter, the first perimeter having a first width measured along a first line and the first width measured along a second line, the first line and the second line each extending through a center of the first perimeter, the first line being perpendicular to the second line in a top down view;
a first underbump metallization extending through a passivation layer to be in physical contact with the first contact pad, the first underbump metallization having a second perimeter, the second perimeter having a second width measured along a third line and a third width measured along a fourth line, the third line and the fourth line each extending through a center of the second perimeter, the third line being perpendicular to the fourth line in the top down view, the second width being greater than the first width, the third width being less than the first width;
a first external contact in connection with the first underbump metallization;
a reflowable material in physical contact with the first external contact; and
a second external contact in physical contact with the reflowable material on an opposite side of the reflowable material from the first external contact.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, further comprising:
a second contact pad over the substrate, the second contact pad having a third perimeter;
a second underbump metallization in physical contact with the second contact pad, the second underbump metallization having a fourth perimeter that crosses the third perimeter at least four times in a top down view; and
a third external contact in connection with the second underbump metallization.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein a pitch between the first external contact and the second external contact is about 80 μm.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, further comprising:
a first redistribution line located between the first external contact and the third external contact; and
a second redistribution line located between the first external contact and the third external contact.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein the first redistribution line has a width of between about 2 μm and about 14.5 μm.

### Claim 20 (depends on 15)

The semiconductor device of claim 15, wherein the first underbump metallization comprises a rectangular shape in a top down view.