# US 10,504,855 B2 · Semiconductor package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,504,855 B2 - Document ID: US10504855B2 - Status: Granted - Kind: B2 - Application number: 16/171,126 - Filed: 2018-10-25 - Published: 2019-11-07 - Granted: 2019-12-10 - Earliest claimed: 2018-05-03 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Kyung Moon Jung; Chul Kyu Kim; Seok Hwan Kim; Kyung Ho Lee; Seong Hwan Park - Web page: https://patentgrep.com/patent/US10504855B2 ## CPC - H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 20/42: Vias, e.g. via plugs - H10W 42/284: {shielding resins} - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/635: {Through-vias} - H10W 72/90: Bond pads, in general - H10W 74/114: {by a substrate and the encapsulations} - H10W 90/00: Package configurations - H10W 70/655: Fan-out layouts - H10W 70/656: Fan-in layouts - H10W 70/657: {on sidewalls or bottom surfaces of the package substrates, interposers or redistribution layers} - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 76/13: Containers comprising a conductive base serving as an interconnection - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package includes a support member having a first surface and a second surface, and having a through-hole, a first metal layer for shielding disposed on an internal sidewall of the through-hole and the first surface and the second surface of the support member, a connection member disposed on the first surface of the support member, and having a redistribution layer, a semiconductor chip disposed in the through-hole, an encapsulant sealing the semiconductor chip located in the through-hole, and covering the second surface of the support member, a second metal layer for shielding disposed on the encapsulant, and connected to the first metal layer for shielding by a connecting trench via passing through the encapsulant, and a reinforcing via disposed in a region, overlapping the trench via for connection, of the support member, and connected to the first metal layer for shielding. ## Claims ### Claim 1 A semiconductor package, comprising: a support member having a first surface and a second surface opposing each other, and having a through-hole; a first metal layer disposed on an internal sidewall of the through-hole and the first surface and the second surface of the support member; a connection member disposed on the first surface of the support member, and having a redistribution layer; a semiconductor chip disposed in the through-hole, and having a connection pad connected to the redistribution layer; an encapsulant sealing the semiconductor chip located in the through-hole, and covering the second surface of the support member; a second metal layer disposed on the encapsulant, and connected to the first metal layer by a connecting trench via passing through the encapsulant; and a reinforcing via disposed in a region, overlapping the connecting trench via, of the support member, and connected to the first metal layer. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the reinforcing via includes a plurality of vias arranged along the region which overlaps the connecting trench via. ### Claim 3 (depends on 1) The semiconductor package of claim 1, wherein the reinforcing via has a single trench structure extending along the region which overlaps the connecting trench via. ### Claim 4 (depends on 3) The semiconductor package of claim 3, wherein the reinforcing via has a plurality of trench structures spaced apart at predetermined intervals along the region which overlaps the connecting trench via. ### Claim 5 (depends on 1) The semiconductor package of claim 1, wherein the reinforcing via has a trapezoidal shape when viewed in a cross-section in a thickness direction of the support member. ### Claim 6 (depends on 1) The semiconductor package of claim 1, wherein the reinforcing via is connected to a metal pattern located in the support member. ### Claim 7 (depends on 1) The semiconductor package of claim 1, wherein the connecting trench via surrounds the through-hole in a plan view perpendicular to a thickness direction of the support member. ### Claim 8 (depends on 1) The semiconductor package of claim 1, further comprising: a shielding via surrounding the connection member in a region, adjacent to an edge, of the connection member, and connected to the first metal layer. ### Claim 9 (depends on 8) The semiconductor package of claim 8, wherein the shielding via is formed of a material the same as a material of the redistribution layer. ### Claim 10 (depends on 1) The semiconductor package of claim 1, further comprising: a heat dissipating device disposed in a region, corresponding to the semiconductor chip, of the connection member. ### Claim 11 (depends on 1) The semiconductor package of claim 1, wherein the reinforcing via includes a first via and a second via, located in a region adjacent to the region which overlaps the connecting trench via, and surrounding the through-hole. ### Claim 12 A semiconductor package, comprising: a support member having a first surface and a second surface opposing each other, and having a first through-hole and a second through-hole; a first metal layer disposed on at least an internal sidewall of the second through-hole and the first surface and the second surface of the support member; a connection member disposed on the first surface of the support member, and having a redistribution layer; a semiconductor chip disposed in the first through-hole, and having a connection pad connected to the redistribution layer; at least one passive component disposed in the second through-hole, and having a connection terminal connected to the redistribution layer; an encapsulant sealing the semiconductor chip and the at least one passive component, and covering the second surface of the support member; a second metal layer disposed on the encapsulant; a connecting trench via passing through the encapsulant to connect the first metal layer to the second metal layer, and surrounding the first through-hole and the second through-hole in a plan view perpendicular to a thickness direction of the support member; and a reinforcing via disposed in at least a portion of a region, overlapping the connecting trench via, of the support member, and connected to the first metal layer. ### Claim 13 (depends on 12) The semiconductor package of claim 12, wherein the connecting trench via has a portion disposed along a region adjacent to an outer edge of the support member, and the reinforcing via has a portion disposed along a region adjacent to the outer edge of the support member. ### Claim 14 (depends on 12) The semiconductor package of claim 12, further comprising: a shielding via surrounding the connection member in a region, adjacent to an edge, of the connection member, and having a via stack structure connected to the first metal layer.