# US 10,504,854 B2 · Through-stiffener inerconnects for package-on-package apparatus and methods of assembling same

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- Number: US 10,504,854 B2
- Document ID: US10504854B2
- Status: Granted
- Kind: B2
- Application number: 16/018,984
- Filed: 2018-06-26
- Published: 2019-06-13
- Granted: 2019-12-10
- Earliest claimed: 2017-12-07
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Bok Eng Cheah; Seok Ling Lim; Jenny Shio Yin Ong; Jackson Chung Peng Kong
- Web page: https://patentgrep.com/patent/US10504854B2

## CPC

- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 42/267: {Patterned shielding planes}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 76/40: Fillings or auxiliary members in containers, e.g. centering rings (fillings or auxiliary members for thermal protection or control in containers or encapsulations H10W40/70)
- H10W 90/00: Package configurations
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/63: Vias, e.g. via plugs
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 72/07254: {changes in dispositions}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A stiffener includes a through-stiffener interconnect that couples a semiconductor package substrate to a package-on-package device. The through-stiffener interconnect is insulated by a through-stiffener dielectric within a through-stiffener contact corridor. A semiconductive die is coupled to the semiconductor package substrate and to the package-on-package device.

## Claims

### Claim 1

A semiconductor package, comprising:
a semiconductor package substrate including a die side and a land side;
a through-stiffener interconnect (TSI) stiffener disposed on the die side, wherein the TSI stiffener includes a die side and a package-on-package (POP) side, and wherein the TSI stiffener includes a TSI that communicates from the die side to the POP side, wherein the TSI is electrically insulated with a TSI dielectric;
an electrical connection between the package substrate and the TSI;
a subsequent stiffener disposed on the die side, wherein the TSI stiffener surrounds the subsequent stiffener; and
a passive device bridging between the TSI stiffener and the subsequent stiffener, wherein the TSI stiffener is coupled to a source voltage structure within the semiconductor package substrate.

### Claim 2

A computing system, comprising:
a semiconductor package substrate including a die side and a land side;
a semiconductive die disposed on the die side;
a stiffener disposed on the die side, wherein the stiffener includes a die side and a package-on-package (POP) side, and wherein the stiffener includes a first through-stiffener interconnect (TSI) that communicates from the die side to the POP side;
an electrical connection between the package substrate and the first TSI, wherein the first TSI is located on the stiffener on a first rail portion;
a POP device seated on the stiffener, wherein the POP device is coupled to the first TSI;
a subsequent TSI located in the stiffener on a subsequent rail portion that is opposite the first rail portion, wherein the subsequent TSI electrically contacts the semiconductor package substrate and the POP device;
a third rail portion between the first and subsequent rail portions, and a fourth rail portion opposite the third rail portion; and
a board at which the land side is mounted by at least one electrical bump, and wherein the board includes a dielectric outer shell.

### Claim 3 (depends on 2)

The computing system of claim 2, further including:
a subsequent semiconductive die disposed above the semiconductor package substrate die side, wherein the subsequent semiconductive die is electrically coupled to the semiconductor package substrate by a face-to-face connection with the first semiconductive die and a through-silicon via (TSV) through the first semiconductive die, wherein the first semiconductive die is a platform controller hub, and wherein the subsequent semiconductive die is a logic processor;
a memory die disposed in the POP device, wherein the memory die is wirebonded and coupled to the TSI; and
wherein the platform controller hub is part of a chipset.

### Claim 4

A semiconductor package, comprising:
a semiconductor package substrate including a die side and a land side;
a stiffener disposed on the die side, wherein the stiffener includes a die side and a package-on-package (POP) side, and wherein the stiffener includes a first through-stiffener interconnect (TSI) that communicates from the die side to the POP side, wherein the first TSI is electrically insulated with a TSI dielectric, and wherein the first TSI is on a first rail portion of the stiffener;
an electrical connection between the package substrate and the first TSI, wherein the electrical connection is coupled to at least one of a power or input/output (I/O) connection, further including wherein the stiffener also is coupled to the semiconductor package substrate at a source voltage structure;
a subsequent TSI located in the stiffener on a subsequent rail portion that is opposite the first rail portion; and
a semiconductive die disposed on the semiconductor package substrate die side, wherein the semiconductive die is coupled to the first TSI
a board at which the land side is mounted by at least one electrical bump, and wherein the board includes a dielectric outer shell; and
wherein the semiconductive die is a first semiconductive die, and further including a subsequent semiconductive die disposed above the semiconductor package substrate die side, and wherein the first semiconductive die and the subsequent semiconductive die are part of a chipset.