# US 10,504,850 B2 · Semiconductor processing method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,504,850 B2 - Document ID: US10504850B2 - Status: Granted - Kind: B2 - Application number: 15/752,728 - Filed: 2016-08-12 - Published: 2018-08-16 - Granted: 2019-12-10 - Earliest claimed: 2015-08-14 - Assignees: Pep Innovation Pte. Ltd. - Applicants: Pep Innovation Pte Ltd - Inventors: Yi Xin Chew - Web page: https://patentgrep.com/patent/US10504850B2 ## CPC - H10W 46/00: Marks applied to devices, e.g. for alignment or identification - H10P 72/74: {using temporarily an auxiliary support} - H10W 72/00: Interconnections or connectors in packages - H10W 74/114: {by a substrate and the encapsulations} - H10W 78/00: Detachable holders for supporting packaged chips in operation - H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto} - H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer} - H10W 46/101: {characterised by the type of information, e.g. logos or symbols} - H10W 46/301: {for alignment} - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/655: Fan-out layouts - H10W 72/01323: {in liquid form, e.g. by dispensing droplets or by screen printing} - H10W 72/01336: {in solid form, e.g. by using a powder or by laminating a foil} - H10W 72/0198: {batch processes} - H10W 72/073: {of die-attach connectors} - H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate} - H10W 72/07338: {hardening the adhesive by curing, e.g. thermosetting} - H10W 72/325: {Die-attach connectors having a filler embedded in a matrix} - H10W 72/351: {Materials of die-attach connectors} - H10W 72/352: {comprising metals or metalloids, e.g. solders} - H10W 72/354: {comprising polymers} - H10W 72/874: {On different surfaces} - H10W 72/9413: {on encapsulations} - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 90/00: Package configurations - H10W 90/732: {between stacked chips} - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor processing method is provided. The method includes providing a first carrier (10). A first adhesive (18) is provided on the first carrier (10) and a plurality of semiconductor chips (20) is placed on the first adhesive (18). A second carrier (28) is provided. The second carrier (28) is provided with a plurality of chip receiving areas (32). The first and second carriers (10) and (28) are then brought together to attach the semiconductor chips (20) to respective ones of the chip receiving areas (32) on the second carrier (28). The first carrier (10) is then separated from the semiconductor chips (20). ## Claims ### Claim 1 A semiconductor processing method, comprising: providing a first carrier, wherein the first carrier is provided with a plurality of first global marks: providing the first carrier with a plurality of first unit marks, the first unit marks defining a plurality of chip placement positions; providing a first adhesive on the first carrier; aligning a plurality of chip marks on each of a plurality of semiconductor chips with corresponding ones of the first unit marks wherein the chip marks are provided on an active surface of the semiconductor chips; placing respective ones of the semiconductor chips on the first adhesive; providing a second carrier, wherein the second carrier is provided with a plurality of chip receiving areas and a plurality of second global marks; aligning the first global marks with corresponding ones of the second global marks; bringing the first and second carriers together to attach the semiconductor chips to respective ones of the chip receiving areas on the second carrier; and separating the first carrier from the semiconductor chips. ### Claim 2 (depends on 1) The method of claim 1, wherein each of the first global marks has a different shape and each of the second global marks has a same shape as a corresponding one of the first global marks. ### Claim 3 (depends on 1) The method of claim 1, wherein the step of providing the first carrier with the first unit marks comprises determining a position of the first unit marks based on a position of the first global marks. ### Claim 4 (depends on 1) The method of claim 1, wherein the chip receiving areas comprise a plurality of chip pads provided on the second carrier. ### Claim 5 (depends on 4) The method of claim 4, further comprising forming a plurality of second unit marks on one of a surface of the second carrier adjacent respective ones of the chip pads and the chip pads themselves. ### Claim 6 (depends on 5) The method of claim 5, wherein the step of forming the second unit marks comprises determining a position of the second unit marks based on a position of the second global marks. ### Claim 7 (depends on 1) The method of claim 1, further comprising providing a plurality of component pads on the second carrier. ### Claim 8 (depends on 7) The method of claim 7, further comprising attaching a plurality of structural features, a plurality of passive components or a combination thereof to respective ones of the component pads on the second carrier. ### Claim 9 (depends on 1) The method of claim 1, further comprising disposing a second adhesive on one of each of the semiconductor chips and each of the chip receiving areas. ### Claim 10 (depends on 9) The method of claim 9, further comprising heating the second adhesive to a curing temperature of the second adhesive after bringing the first and second carriers together. ### Claim 11 (depends on 1) The method of claim 1, wherein the first adhesive comprises a releasable adhesive material. ### Claim 12 (depends on 11) The method of claim 11, further comprising heating the first adhesive to a release temperature of the releasable adhesive material before separating the first carrier from the semiconductor chips. ### Claim 13 (depends on 1) The method of claim 1, wherein the step of separating the first carrier from the semiconductor chips comprises applying a shear force to the first carrier before pulling the first carrier away from the semiconductor chips. ### Claim 14 (depends on 1) The method of claim 1, further comprising providing the second carrier with a plurality of secondary global marks. ### Claim 15 (depends on 1) The method of claim 1, wherein the second carrier is sized to accommodate more than one of the first carrier. ### Claim 16 (depends on 1) The method of claim 1, wherein the first carrier has a same or a smaller coefficient of thermal expansion than the second carrier. ### Claim 17 (depends on 1) The method of claim 1, further comprising forming a dielectric layer on the second carrier, the dielectric layer encapsulating the semiconductor chips. ### Claim 18 (depends on 17) The method of claim 17, further comprising: determining a position of a plurality of terminal pads on each of the semiconductor chips based on a position of the second global marks; and forming a plurality of openings in the dielectric layer to expose respective ones of the terminal pads. ### Claim 19 (depends on 17) The method of claim 17, further comprising forming a plurality of openings in the dielectric layer to expose respective ones of the second global marks. ### Claim 20 (depends on 1) The method of claim 1, further comprising performing a scanning operation to obtain positional data of a plurality of terminal pads on each of the semiconductor chips. ### Claim 21 A semiconductor processing method, comprising: providing a first carrier, wherein the first carrier is provided with a plurality of first global marks; providing a first adhesive on the first carrier; placing a plurality of semiconductor chips on the first adhesive; providing a second carrier, wherein the second carrier is provided with a plurality of chip receiving areas and a plurality of second global marks, and wherein the chip receiving areas comprise a plurality of chip pads provided on the second carrier; forming a plurality of second unit marks on one of a surface of the second carrier adjacent respective ones of the chip pads and the chip pads themselves; aligning the first global marks with corresponding ones of the second global marks; bringing the first and second carriers together to attach the semiconductor chips to respective ones of the chip receiving areas on the second carrier; and separating the first carrier from the semiconductor chips. ### Claim 22 (depends on 21) The method of claim 21, wherein each of the first global marks has a different shape and each of the second global marks has a same shape as a corresponding one of the first global marks. ### Claim 23 (depends on 21) The method of claim 21, further comprising providing the first carrier with a plurality of first unit marks, the first unit marks defining a plurality of chip placement positions, wherein the step of providing the first carrier with the first unit marks comprises determining a position of the first unit marks based on a position of the first global marks. ### Claim 24 (depends on 21) The method of claim 21, wherein the step of forming the second unit marks comprises determining a position of the second unit marks based on a position of the second global marks. ### Claim 25 (depends on 21) The method of claim 21, further comprising providing a plurality of component pads on the second carrier. ### Claim 26 (depends on 25) The method of claim 25, further comprising attaching a plurality of structural features, a plurality of passive components or a combination thereof to respective ones of the component pads on the second carrier. ### Claim 27 (depends on 25) The method of claim 25, further comprising disposing a second adhesive on one of each of the semiconductor chips and each of the chip receiving areas. ### Claim 28 (depends on 27) The method of claim 27, further comprising heating the second adhesive to a curing temperature of the second adhesive after bringing the first and second carriers together. ### Claim 29 (depends on 21) The method of claim 21, wherein the first adhesive comprises a releasable adhesive material. ### Claim 30 (depends on 29) The method of claim 29, further comprising heating the first adhesive to a release temperature of the releasable adhesive material before separating the first carrier from the semiconductor chips. ### Claim 31 (depends on 21) The method of claim 21, wherein the step of separating the first carrier from the semiconductor chips comprises applying a shear force to the first carrier before pulling the first carrier away from the semiconductor chips. ### Claim 32 (depends on 21) The method of claim 21, further comprising providing the second carrier with a plurality of secondary global marks. ### Claim 33 (depends on 21) The method of claim 21, wherein the second carrier is sized to accommodate more than one of the first carrier. ### Claim 34 (depends on 21) The method of claim 21, wherein the first carrier has a same or a smaller coefficient of thermal expansion than the second carrier. ### Claim 35 (depends on 21) The method of claim 21, further comprising forming a dielectric layer on the second carrier, the dielectric layer encapsulating the semiconductor chips. ### Claim 36 (depends on 35) The method of claim 35, further comprising: determining a position of a plurality of terminal pads on each of the semiconductor chips based on a position of the second global marks; and forming a plurality of openings in the dielectric layer to expose respective ones of the terminal pads. ### Claim 37 (depends on 35) The method of claim 35, further comprising forming a plurality of openings in the dielectric layer to expose respective ones of the second global marks. ### Claim 38 (depends on 21) The method of claim 21, further comprising performing a scanning operation to obtain positional data of a plurality of terminal pads on each of the semiconductor chips. ### Claim 39 A semiconductor processing method, comprising: providing a first carrier, wherein the first carrier is provided with a plurality of first global marks; providing a first adhesive on the first carrier; placing a plurality of semiconductor chips on the first adhesive; providing a second carrier, wherein the second carrier is provided with a plurality of chip receiving areas and a plurality of second global marks; forming a dielectric layer on the second carrier, the dielectric layer encapsulating the semiconductor chips; determining a position of a plurality of terminal pads on each of the semiconductor chips based on a position of the second global marks; forming a plurality of openings in the dielectric layer to expose respective ones of the terminal pads; aligning the first global marks with corresponding ones of the second global marks; bringing the first and second carriers together to attach the semiconductor chips to respective ones of the chip receiving areas on the second carrier; and separating the first carrier from the semiconductor chips. ### Claim 40 (depends on 39) The method of claim 39, wherein each of the first global marks has a different shape and each of the second global marks has a same shape as a corresponding one of the first global marks. ### Claim 41 (depends on 39) The method of claim 39, further comprising providing the first carrier with a plurality of first unit marks, the first unit marks defining a plurality of chip placement positions, wherein the step of providing the first carrier with the first unit marks comprises determining a position of the first unit marks based on a position of the first global marks. ### Claim 42 (depends on 39) The method of claim 39, wherein the chip receiving areas comprise a plurality of chip pads provided on the second carrier, wherein a plurality of second unit marks is formed on one of a surface of the second carrier adjacent respective ones of the chip pads and the chip pads themselves, and wherein a position of the second unit marks is determined based on a position of the second global marks. ### Claim 43 (depends on 39) The method of claim 39, further comprising providing a plurality of component pads on the second carrier. ### Claim 44 (depends on 43) The method of claim 43, further comprising attaching a plurality of structural features, a plurality of passive components or a combination thereof to respective ones of the component pads on the second carrier. ### Claim 45 (depends on 39) The method of claim 39, further comprising disposing a second adhesive on one of each of the semiconductor chips and each of the chip receiving areas. ### Claim 46 (depends on 45) The method of claim 45, further comprising heating the second adhesive to a curing temperature of the second adhesive after bringing the first and second carriers together. ### Claim 47 (depends on 39) The method of claim 39, wherein the first adhesive comprises a releasable adhesive material. ### Claim 48 (depends on 47) The method of claim 47, further comprising heating the first adhesive to a release temperature of the releasable adhesive material before separating the first carrier from the semiconductor chips. ### Claim 49 (depends on 39) The method of claim 39, wherein the step of separating the first carrier from the semiconductor chips comprises applying a shear force to the first carrier before pulling the first carrier away from the semiconductor chips. ### Claim 50 (depends on 39) The method of claim 39, further comprising providing the second carrier with a plurality of secondary global marks. ### Claim 51 (depends on 39) The method of claim 39, wherein the second carrier is sized to accommodate more than one of the first carrier. ### Claim 52 (depends on 39) The method of claim 39, wherein the first carrier has a same or a smaller coefficient of thermal expansion than the second carrier. ### Claim 53 (depends on 39) The method of claim 39, further comprising forming a plurality of openings in the dielectric layer to expose respective ones of the second global marks. ### Claim 54 (depends on 39) The method of claim 39, further comprising performing a scanning operation to obtain positional data of a plurality of terminal pads on each of the semiconductor chips. ### Claim 55 A semiconductor processing method, comprising: providing a first carrier, wherein the first carrier is provided with a plurality of first global marks; providing a first adhesive on the first carrier; placing a plurality of semiconductor chips on the first adhesive; providing a second carrier, wherein the second carrier is provided with a plurality of chip receiving areas and a plurality of second global marks; forming a dielectric layer on the second carrier, the dielectric layer encapsulating the semiconductor chips; forming a plurality of openings in the dielectric layer to expose respective ones of the second global marks; aligning the first global marks with corresponding ones of the second global marks; bringing the first and second carriers together to attach the semiconductor chips to respective ones of the chip receiving areas on the second carrier; and separating the first carrier from the semiconductor chips. ### Claim 56 (depends on 55) The method of claim 55, wherein each of the first global marks has a different shape and each of the second global marks has a same shape as a corresponding one of the first global marks. ### Claim 57 (depends on 55) The method of claim 55, further comprising providing the first carrier with a plurality of first unit marks, the first unit marks defining a plurality of chip placement positions, wherein the step of providing the first carrier with the first unit marks comprises determining a position of the first unit marks based on a position of the first global marks. ### Claim 58 (depends on 55) The method of claim 55, wherein the chip receiving areas comprise a plurality of chip pads provided on the second carrier, wherein a plurality of second unit marks is formed on one of a surface of the second carrier adjacent respective ones of the chip pads and the chip pads themselves, and wherein a position of the second unit marks is determined based on a position of the second global marks. ### Claim 59 (depends on 55) The method of claim 55, further comprising providing a plurality of component pads on the second carrier. ### Claim 60 (depends on 59) The method of claim 59, further comprising attaching a plurality of structural features, a plurality of passive components or a combination thereof to respective ones of the component pads on the second carrier. ### Claim 61 (depends on 55) The method of claim 55, further comprising disposing a second adhesive on one of each of the semiconductor chips and each of the chip receiving areas. ### Claim 62 (depends on 61) The method of claim 61, further comprising heating the second adhesive to a curing temperature of the second adhesive after bringing the first and second carriers together. ### Claim 63 (depends on 55) The method of claim 55, wherein the first adhesive comprises a releasable adhesive material. ### Claim 64 (depends on 63) The method of claim 63, further comprising heating the first adhesive to a release temperature of the releasable adhesive material before separating the first carrier from the semiconductor chips. ### Claim 65 (depends on 58) The method of claim 58, wherein the step of separating the first carrier from the semiconductor chips comprises applying a shear force to the first carrier before pulling the first carrier away from the semiconductor chips. ### Claim 66 (depends on 58) The method of claim 58, further comprising providing the second carrier with a plurality of secondary global marks. ### Claim 67 (depends on 58) The method of claim 58, wherein the second carrier is sized to accommodate more than one of the first carrier. ### Claim 68 (depends on 58) The method of claim 58, wherein the first carrier has a same or a smaller coefficient of thermal expansion than the second carrier. ### Claim 69 (depends on 58) The method of claim 58, further comprising performing a scanning operation to obtain positional data of a plurality of terminal pads on each of the semiconductor chips.