# US 10,504,848 B1 · Chip embedded integrated voltage regulator > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,504,848 B1 - Document ID: US10504848B1 - Status: Granted - Kind: B1 - Application number: 16/279,814 - Filed: 2019-02-19 - Granted: 2019-12-10 - Earliest claimed: 2019-02-19 - Assignees: Faraday Semi, Inc. - Applicants: Faraday Semi, Inc. - Inventors: Parviz Parto - Web page: https://patentgrep.com/patent/US10504848B1 ## CPC - H10W 70/614: {the multiple chips being integrally enclosed} - G06F 1/3287: by switching off individual functional units in the computer system - G06F 1/3296: by lowering the supply or operating voltage - H02M 3/158: including plural semiconductor devices as final control devices for a single load - H02M 3/1584: {with a plurality of power processing stages connected in parallel} - H10D 1/20: Inductors - H10W 44/501: {Inductive arrangements (H10W44/20 takes precedence)} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/611: {for connecting multiple chips together} - H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers} - H10W 70/685: comprising multiple insulating layers - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H02M 1/007: {Plural converter units in cascade (push-pull DC/DC converters with pre-regulator H02M3/3374; DC-AC converters following a DC-DC stage including a high frequency transformer H02M7/4807; DC-AC converters following a DC-DC conversion stage generating periodically varying voltages H02M7/4826)} - H02M 1/08: Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters - H02M 3/003: {Constructional details, e.g. physical layout, assembly, wiring or busbar connections} - H05K 1/181: associated with surface mounted components - H05K 1/185: associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards - H05K 2201/1003: Non-printed inductor - H05K 2201/10166: Transistor - H05K 2201/10378: Interposers - H10W 70/63: Vias, e.g. via plugs - H10W 70/6528: {of the portions that connect to chips, wafers or package parts} - H10W 72/874: {On different surfaces} - H10W 72/9413: {on encapsulations} - H10W 90/00: Package configurations - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract One or more chip-embedded integrated voltage regulators (“CEIVR's”) are configured to provide power to a circuit or chip such as a CPU or GPU and meet power delivery specifications. The CEIVR's, circuit or chip, and power delivery pathways can be included within the same package. The CEIVR's can be separate from the circuit or chip. ## Claims ### Claim 1 A method for delivering electrical power, the method comprising: receiving electrical power having a first voltage; modifying the electrical power using a power converter to provide electrical power having a second voltage lower than the first voltage; delivering the electrical power having the second voltage to a processor package that comprises: an interposer; a computer processor mounted onto the interposer; and a plurality of chip-embedded voltage regulators on the interposer, wherein the plurality of chip-embedded voltage regulators are coupled in parallel and are electrically coupled to the computer processor through the interposer, and wherein each of the plurality of chip-embedded voltage regulators comprises: chip-embedded circuitry including a plurality of power switches configured to modify electrical power; and an inductor coupled to the chip-embedded circuitry, wherein a footprint of the inductor at least partially overlaps a footprint of the chip-embedded circuitry; modifying the electrical power provided to the processor package using the plurality of chip-embedded voltage regulators to provide electrical power having a third voltage lower than the second voltage; and delivering the electrical power having the third voltage to the computer processor through the interposer. ### Claim 2 (depends on 1) The method of claim 1, wherein the plurality of chip-embedded voltage regulators have a multiple power stage topology. ### Claim 3 (depends on 1) The method of claim 1, further comprising: receiving communications in I2C or PMBUS protocol communications, and in response, performing at least one of: changing a setting of at least one of the plurality of chip-embedded voltage regulators; or reporting information about at least one of the plurality of chip-embedded voltage regulators. ### Claim 4 (depends on 1) The method of claim 1, wherein the third voltage is about 0.4 V to about 1 V. ### Claim 5 (depends on 4) The method of claim 4, wherein the second voltage is about 1 V to about 4 V. ### Claim 6 (depends on 1) The method of claim 1, wherein the inductor is a thin film inductor. ### Claim 7 (depends on 1) The method of claim 1, wherein the inductor is embedded with the chip-embedded circuitry. ### Claim 8 (depends on 1) The method of claim 1, wherein the chip-embedded circuitry comprises: a pulse width modulator (PWM) controller configured to generate one or more PWM signals; and a driver configured to generate one or more driver signals based at least in part on the one or more PWM signals, wherein the plurality of power switches are driven by the one or more driver signals. ### Claim 9 (depends on 1) The method of claim 1, wherein the chip-embedded circuitry is embedded in a substrate of the interposer. ### Claim 10 (depends on 1) The method of claim 1, wherein the chip-embedded circuitry is embedded in a printed circuit board (PCB) between an upper PCB part and a lower PCB part. ### Claim 11 (depends on 10) The method of claim 10, wherein the PCB is mounted onto the interposer. ### Claim 12 A packaged electronic device comprising: a semiconductor die in a package; a package substrate coupled to the semiconductor die and coupling the semiconductor die to package outputs; and a chip-embedded power converter that is separate from the semiconductor die, wherein the power converter includes: an input port configured to receive an input power; an output port; chip-embedded circuitry including a plurality of power switches configured to cause a modified power to be provided at the output port; an inductor coupled to the plurality of power switches; and an output capacitor coupled to the plurality of power switches; wherein the power converter is configured to deliver the modified power within the package to the semiconductor die; and wherein the semiconductor die, the package substrate, and the power converter are included in the same package. ### Claim 13 (depends on 12) The packaged electronic device of claim 12, wherein the chip-embedded power converter has at least one of a multiple phase or an AC coupled topology. ### Claim 14 (depends on 12) The packaged electronic device of claim 12, wherein: the power converter is a direct-current to direct-current (DC-DC) chip-embedded power converter; and the plurality of power switches are embedded in a printed circuit board (PCB). ### Claim 15 (depends on 12) The packaged electronic device of claim 12, wherein the semiconductor die includes a semiconductor processor. ### Claim 16 (depends on 12) The packaged electronic device of claim 12, wherein the inductor is a thin-film inductor. ### Claim 17 (depends on 12) The packaged electronic device of claim 12, wherein: a footprint of the inductor overlaps a footprint of the plurality of power switches; and the plurality of power switches are coupled through one or more vias extending through at least a portion of a PCB to the inductor. ### Claim 18 (depends on 12) The packaged electronic device of claim 12, wherein the plurality of power switches comprise gallium nitride (GaN) or enhanced gallium nitride (eGaN) power switches. ### Claim 19 (depends on 12) The packaged electronic device of claim 12, comprising a plurality of chip-embedded power converters that are coupled to each other and coupled to the package substrate. ### Claim 20 (depends on 19) The packaged electronic device of claim 19 wherein the plurality of chip-embedded power converters are coupled in parallel. ### Claim 21 (depends on 19) The packaged electronic device of claim 19, further comprising: one or more communication pathways between the semiconductor die and the plurality of chip-embedded power converters, wherein the semiconductor die is configured to enable or disable individual chip-embedded power converters of the plurality of chip-embedded power converters using the one or more communication pathways. ### Claim 22 (depends on 19) The packaged electronic device of claim 19, further comprising: a load balancing circuit configured to adjust current sharing across the plurality of chip-embedded power converters. ### Claim 23 (depends on 12) The packaged electronic device of claim 12, wherein the semiconductor die comprises a processor, and wherein the package substrate is an interposer associated with the processor. ### Claim 24 A method for assembling a chip-embedded integrated voltage regulator for a package, the method comprising: providing a package substrate having an electrical connection arrangement for coupling a first semiconductor die to at least one of package inputs or package outputs; providing a chip-embedded power converter within the package, wherein the chip-embedded power converter includes at least power switches in a second semiconductor die that is chip-embedded; and coupling, within the package, an output of the chip-embedded power converter to provide power to the first semiconductor die. ### Claim 25 (depends on 24) The method of claim 24, wherein the chip-embedded power converter has an isolated topology including at least one of: a flyback topology, a forward converter topology, a two transistor forward topology, push-pull topology, full bridge topology, hybrid typology, and half bridge topology. ### Claim 26 (depends on 24) The method of claim 24, wherein the second semiconductor die is chip-embedded within a printed circuit board (PCB) that is mounted onto the package substrate. ### Claim 27 (depends on 24) The method of claim 24, wherein the second semiconductor die is chip-embedded in the package substrate. ### Claim 28 (depends on 24) The method of claim 24, wherein: the first semiconductor die is a silicon based semiconductor die; and the second semiconductor die that includes the power switches is an enhanced gallium nitride (eGaN) semiconductor die. ### Claim 29 (depends on 24) The method of claim 24, further comprising: coupling an arrangement of a plurality of chip-embedded power converters within the package to the package substrate, each of the plurality of chip-embedded power converters configured to provide power within the package to the first semiconductor die, the chip-embedded power converter being included in the arrangement. ### Claim 30 (depends on 29) The method of claim 29, further comprising: performing load balancing among the plurality of chip-embedded power converters by adjusting a current output by at least one of the plurality of chip-embedded power converters.