# US 10,504,847 B2 · Chip package structure and chip package structure array > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,504,847 B2 - Document ID: US10504847B2 - Status: Granted - Kind: B2 - Application number: 15/842,822 - Filed: 2017-12-14 - Published: 2019-05-09 - Granted: 2019-12-10 - Earliest claimed: 2017-11-09 - Assignees: Shanghai Zhaoxin Semiconductor Co., Ltd. - Applicants: Shanghai Zhaoxin Semiconductor Co., Ltd. - Inventors: Wen-Yuan Chang; Yeh-Chi Hsu; Hsueh-Chung Shelton Lu; Wei-Cheng Chen - Web page: https://patentgrep.com/patent/US10504847B2 ## CPC - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 40/10: Arrangements for heating - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/611: {for connecting multiple chips together} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/685: comprising multiple insulating layers - H10W 72/0198: {batch processes} - H10W 74/01: Manufacture or treatment - H10W 74/014: {using batch processing} - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 74/129: {forming a chip-scale package [CSP]} - H10W 76/40: Fillings or auxiliary members in containers, e.g. centering rings (fillings or auxiliary members for thermal protection or control in containers or encapsulations H10W40/70) - H10W 90/00: Package configurations - H10W 99/00: Subject matter not provided for in other groups of this subclass - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/6528: {of the portions that connect to chips, wafers or package parts} - H10W 72/07207: {Temporary substrates, e.g. removable substrates} - H10W 72/227: {Multiple bumps having different sizes} - H10W 72/248: {Top-view layouts, e.g. mirror arrays} - H10W 72/853: {On the same surface} - H10W 72/874: {On different surfaces} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 90/10: Configurations of laterally-adjacent chips - H10W 90/288: {characterised by arrangements for thermal management of the stacked chips} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A chip package structure includes a plurality of first chips, a plurality of first conductive pillars, a second chip, a plurality of second conductive pillars, an encapsulated material and a redistribution structure. Each first chip has a first active surface. Each of the first conductive pillars is disposed on the first active surface of the corresponding first chip. A second active surface of the second chip is electrically connected to the first active surfaces of the first chips through the second conductive pillars. The encapsulated material partially covers the first chips, the first conductive pillars, the second chip and the second conductive pillars. The redistribution structure is disposed on the encapsulated material and connects the first conductive pillars. A chip package structure array is also provided. ## Claims ### Claim 1 A chip package structure, comprising: a plurality of first chips, each of the first chips having a first active surface; a plurality of first conductive pillars, each of the first conductive pillars being disposed on the first active surface of the corresponding first chip; a second chip, having a second active surface, and the second chip is an one-side connect die; a plurality of second conductive pillars, each of the second conductive pillars is connected between the first active surface of the corresponding first chip and the second active surface of the corresponding second chip, the second chip is electrically connected to the first active surfaces of the first chips only through the second conductive pillars, and a height of the first conductive pillars with respect to the first active surface is larger than a height of the second chip and the second conductive pillars with respect to the first active surface; an encapsulated material, covering the first chips, the second chip and the second conductive pillars, and partially covering the first conductive pillars; and a redistribution structure, disposed on the encapsulated material and connecting with the first conductive pillars, wherein a part of the encapsulated material is located between the second chip and the redistribution structure. ### Claim 2 (depends on 1) The chip package structure as recited in claim 1, wherein a distribution density of the second conductive pillars is greater than a distribution density of the first conductive pillars. ### Claim 3 (depends on 1) The chip package structure as recited in claim 1, wherein an orthographic projection area of the second conductive pillars on the first chips is less than or equal to an orthographic projection area of the first conductive pillars on the first chips. ### Claim 4 (depends on 1) The chip package structure as recited in claim 1, wherein a height of the second conductive pillars with respect to the first active surface is less than or equal to a height of the first conductive pillars with respect to the first active surface. ### Claim 5 (depends on 1) The chip package structure as recited in claim 1, wherein the first chips are electrically connected to each other through the redistribution structure. ### Claim 6 (depends on 1) The chip package structure as recited in claim 1, further comprising: a carrier, wherein the carrier is made of a heat dissipation material and serves as a heat dissipation element, and the first chips and the encapsulated material are disposed on the carrier. ### Claim 7 (depends on 1) The chip package structure as recited in claim 1, further comprising: a supporting structure, surrounding the first chips and embedded in the encapsulated material, and a part of the encapsulated material is located between the supporting structure and the redistribution structure. ### Claim 8 (depends on 7) The chip package structure as recited in claim 7, wherein the supporting structure is exposed at one side of the encapsulated material. ### Claim 9 (depends on 7) The chip package structure as recited in claim 7, further comprising: a carrier, wherein the carrier is made of a heat dissipation material and serves as a heat dissipation element, and the first chips, the encapsulated material and the supporting structure are disposed on the carrier. ### Claim 10 (depends on 9) The chip package structure as recited in claim 9, wherein the supporting structure is exposed at one side of the encapsulated material and one side of the carder. ### Claim 11 (depends on 1) The chip package structure as recited in claim 1, wherein the redistribution structure comprises a plurality of patterned conductive layers, a plurality of dielectric layers, and a plurality of conductive vias, wherein the plurality of dielectric layers and the patterned conductive layers are alternately stacked to one another, and each of the conductive vias is located in the corresponding dielectric layer and electrically connected to the corresponding patterned conductive layers. ### Claim 12 (depends on 1) The chip package structure as recited in claim 1, further comprising: a plurality of conductive contacts, wherein the redistribution structure has a plurality of redistribution pads, and the conductive contacts are respectively disposed on the redistribution pads. ### Claim 13 A chip package structure array, comprising: a plurality of chip package structures, adapted to be arranged in array and form the chip package structure array, each of the chip package structures comprises: a plurality of first chips, each of the first chips having a first active surface; a plurality of first conductive pillars, each of the first conductive pillars being disposed on the first active surface of the corresponding first chip; a second chip, having a second active surface, and the second chip is an one-side connect die; a plurality of second conductive pillars, each of the second conductive pillars is connected between the first active surface of the corresponding first chip and the second active surface of the corresponding second chip, the second chip is electrically connected to the first active surfaces of the first chips only through the second conductive pillars, and a height of the first conductive pillars with respect to the first active surface is larger than a height of the second chip and the second conductive pillars with respect to the first active surface; an encapsulated material, covering the first chips, the second chip and the second conductive pillars, and partially covering the first conductive pillars; and a redistribution structure, disposed on the encapsulated material and connecting with the first conductive pillars, wherein a part of the encapsulated material is located between the second chip and the redistribution structure. ### Claim 14 (depends on 13) The chip package structure array as recited in claim 13, wherein a distribution density of the second conductive pillars is greater than a distribution density of the first conductive pillars. ### Claim 15 (depends on 13) The chip package structure array as recited in claim 13, wherein an orthographic projection area of the second conductive pillars on the first chips is less than or equal to an orthographic projection area of the first conductive pillars on the first chips. ### Claim 16 (depends on 13) The chip package structure array as recited in claim 13, wherein a height of the second conductive pillars with respect to the first active surface is less than or equal to a height of the first conductive pillars with respect to the first active surface. ### Claim 17 (depends on 13) The chip package structure array as recited in claim 13, wherein the first chips are electrically connected to each other through the redistribution structure. ### Claim 18 (depends on 13) The chip package structure array as recited in claim 13, wherein the chip package structure further comprises: a carrier, wherein the carrier is made of a heat dissipation material and serves as a heat dissipation element, and the first chips and the encapsulated material are disposed on the carrier. ### Claim 19 (depends on 13) The chip package structure array as recited in claim 13, wherein the chip package structure further comprises: a supporting structure, surrounding the first chips and embedded in the encapsulated material, and a part of the encapsulated material is located between the supporting structure and the redistribution structure. ### Claim 20 (depends on 19) The chip package structure array as recited in claim 19, wherein the chip package structure further comprises: a carrier, wherein the carrier is made of a heat dissipation material and serves as a heat dissipation element, and the first chips, the encapsulated material and the supporting structure are disposed on the carrier. ### Claim 21 (depends on 13) The chip package structure array as recited in claim 13, wherein the redistribution structure comprises a plurality of patterned conductive layers, a plurality of dielectric layers, and a plurality of conductive vias, wherein the dielectric layers and the patterned conductive layers are alternately stacked to one another, and each of the conductive vias is located in the corresponding dielectric layer and electrically connected to the corresponding patterned conductive layers. ### Claim 22 (depends on 13) The chip package structure array as recited in claim 13, wherein the chip package structure further comprises: a plurality of conductive contacts, wherein the redistribution structure has a plurality of redistribution pads, and the conductive contacts are respectively disposed on the redistribution pads.