# US 10,504,845 B2 · Method for building up a fan-out RDL structure with fine pitch line-width and line-spacing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,504,845 B2 - Document ID: US10504845B2 - Status: Granted - Kind: B2 - Application number: 15/955,395 - Filed: 2018-04-17 - Published: 2018-08-16 - Granted: 2019-12-10 - Earliest claimed: 2014-06-16 - Assignees: STATS ChipPAC Pte. Ltd. - Applicants: STATS ChipPAC Pte. Ltd. - Inventors: Yaojian Lin - Web page: https://patentgrep.com/patent/US10504845B2 ## CPC - H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants - H10W 20/082: {the openings being tapered via holes} - H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning} - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/0198: {batch processes} - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 20/081: {by forming openings in the dielectric parts} - H10W 70/6528: {of the portions that connect to chips, wafers or package parts} - H10W 72/019: {of bond pads} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/9413: {on encapsulations} - H10W 74/014: {using batch processing} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation} - H10W 74/124: {the encapsulations having cavities other than that occupied by chips} - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first insulating layer is formed over a first surface of the encapsulant and an active surface of the semiconductor die. A second insulating layer is formed over a second surface of the encapsulant opposite the first surface. A conductive layer is formed over the first insulating layer. The conductive layer includes a line-pitch or line-spacing of less than 5 μm. The active surface of the semiconductor die is recessed within the encapsulant. A third insulating layer is formed over the semiconductor die including a surface of the third insulating layer coplanar with a surface of the encapsulant. The second insulating layer is formed prior to forming the conductive layer. A trench is formed in the first insulating layer. The conductive layer is formed within the trench. ## Claims ### Claim 1 A semiconductor device, comprising: a semiconductor die; a first insulating layer formed over an active surface of the semiconductor die including a first opening formed through the first insulating layer and elongated in a first direction parallel to the active surface of the semiconductor die, wherein a length of the first opening in the first direction is greater than a width of the first opening in a second direction parallel to the active surface of the semiconductor die, and the second direction is perpendicular to the first direction; a second insulating layer formed over the active surface of the semiconductor die including a second opening formed through the second insulating layer and elongated in the second direction, wherein a length of the second opening in the second direction is greater than a width of the second opening in the first direction, wherein the length of the second opening in the second direction is greater than the width of the first opening in the second direction, and wherein the width of the second opening in the first direction is less than the length of the first opening in the first direction; an encapsulant deposited over the semiconductor die; a backside insulating layer formed over the encapsulant opposite the active surface of the semiconductor die; a third insulating layer formed over the semiconductor die, first insulating layer, second insulating layer, and encapsulant, wherein the third insulating layer extends into the first opening and second opening and includes a third opening formed in the third insulating layer through the first opening and second opening; and a conductive layer formed over the third insulating layer and contacting the active surface of the semiconductor die through the third opening, wherein a surface of the conductive layer that is oriented away from the semiconductor die is coplanar with a surface of the third insulating layer. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the encapsulant covers a back surface of the semiconductor die opposite the active surface. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the conductive layer extends through the first opening and second opening without contacting the first insulating layer or second insulating layer. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein the conductive layer includes a line-pitch or line-spacing of less than 5 μm. ### Claim 5 A semiconductor device, comprising: a semiconductor die; a first insulating layer formed over an active surface of the semiconductor die including a first opening through the first insulating layer elongated in a first direction parallel to the active surface of the semiconductor die, wherein the first opening includes a length of the first opening in the first direction that is greater than a width of the first opening in a second direction perpendicular to the first direction and parallel to the active surface of the semiconductor die; a second insulating layer formed over the active surface of the semiconductor die including a second opening through the second insulating layer and elongated in the second direction, wherein a length of the second opening in the second direction is greater than the width of the first opening in the second direction, and wherein a width of the second opening in the first direction is less than the length of the first opening in the first direction; an encapsulant deposited over the semiconductor die; a build-up interconnect structure formed over the encapsulant and the active surface of the semiconductor die, wherein the build-up interconnect structure includes a third insulating layer extending into the first opening and second opening with a third opening formed in the third insulating layer; and a backside insulating layer formed over the encapsulant opposite the active surface of the semiconductor die, wherein the encapsulant extends between the backside insulating layer and encapsulant. ### Claim 6 (depends on 5) The semiconductor device of claim 5, further including an interconnect component disposed in the encapsulant adjacent to the semiconductor die. ### Claim 7 (depends on 5) The semiconductor device of claim 5, wherein a footprint of the third opening is completely contained within a footprint of the first opening and a footprint of the second opening. ### Claim 8 (depends on 7) The semiconductor device of claim 7, wherein the build-up interconnect structure further includes a conductive layer deposited in the third opening. ### Claim 9 A semiconductor device, comprising: a semiconductor die; a first insulating layer formed over an active surface of the semiconductor die including a first opening formed through the first insulating layer and elongated in a first direction parallel to the active surface of the semiconductor die, wherein a length of the first opening in the first direction is greater than a width of the first opening in a second direction perpendicular to the first direction, and wherein the second direction is parallel to the active surface of the semiconductor die; a second insulating layer formed over the active surface of the semiconductor die including a second opening formed through the second insulating layer and elongated in the second direction, wherein a width of the second opening in the first direction is less than the length of the first opening in the first direction; and a conductive layer formed over the first insulating layer and second insulating layer, wherein a contact pad of the conductive layer is formed directly over the first opening and second opening and the contact pad is elongated in the first direction. ### Claim 10 (depends on 9) The semiconductor device of claim 9, further including an encapsulant deposited over the semiconductor die. ### Claim 11 (depends on 10) The semiconductor device of claim 10, further including an interconnect component disposed in the encapsulant adjacent to the semiconductor die. ### Claim 12 (depends on 10) The semiconductor device of claim 10, wherein a surface of the second insulating layer is coplanar with a surface of the encapsulant. ### Claim 13 (depends on 10) The semiconductor device of claim 10, further including a backside insulating layer formed over the encapsulant, wherein the backside insulating layer includes a resistance to wear greater than a resistance to wear of the encapsulant. ### Claim 14 A semiconductor device, comprising: a semiconductor die; a first insulating layer formed over an active surface of the semiconductor die including a first opening through the first insulating layer and elongated in a first direction parallel to the active surface of the semiconductor die, wherein a length of the first opening in the first direction is greater than a width of the first opening in a second direction parallel to the active surface of the semiconductor die, and the second direction is perpendicular to the first direction; and a second insulating layer formed over the active surface of the semiconductor die including a second opening formed through the second insulating layer and elongated in the second direction, wherein a length of the second opening in the second direction is greater than a width of the second opening in the first direction, and wherein the width of the second opening in the first direction is less than the length of the first opening in the first direction; and a conductive layer in contact with the semiconductor die through the first opening and second opening, wherein the conductive layer extends through the first opening and second opening without contacting the first insulating layer or second insulating layer. ### Claim 15 (depends on 14) The semiconductor device of claim 14, wherein the conductive layer includes a line-pitch or line-spacing of less than 5 μm. ### Claim 16 (depends on 14) The semiconductor device of claim 14, further including a third insulating layer formed over the first insulating layer and second insulating layer, wherein the conductive layer is formed in a trench of the third insulating layer. ### Claim 17 (depends on 1) The semiconductor device of claim 1, wherein the conductive layer contacts the encapsulant. ### Claim 18 (depends on 1) The semiconductor device of claim 1, wherein the conductive layer includes a conductive trace. ### Claim 19 (depends on 8) The semiconductor device of claim 8, wherein a surface of the conductive layer oriented away from the semiconductor die is coplanar with a surface of the third insulating layer.