# US 10,504,842 B1 · Semiconductor device including superconducting metal through-silicon-vias

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- Number: US 10,504,842 B1
- Document ID: US10504842B1
- Status: Granted
- Kind: B1
- Application number: 16/001,302
- Filed: 2018-06-06
- Granted: 2019-12-10
- Earliest claimed: 2017-05-31
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: David W. Abraham; John M. Cotte
- Web page: https://patentgrep.com/patent/US10504842B1

## CPC

- H10W 20/4484: {Superconducting materials}
- H10P 14/40: of conductive or resistive materials
- H10P 14/47: Electrolytic deposition, i.e. electroplating; Electroless plating
- H10P 50/264: {by chemical means}
- H10P 70/27: {during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0238: {comprising etching via holes through pads or through electrodes}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/0261: {characterised by the filling method or the material of the conductive fill}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 90/00: Package configurations
- H10W 72/00: Interconnections or connectors in packages
- H10W 80/334: {Thermocompression bonding}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure and methods of forming the semiconductor structure generally includes providing a thermocompression bonded superconducting metal layer sandwiched between a first silicon substrate and a second silicon substrate. The second substrate includes a plurality of through silicon vias to the thermocompression bonded superconducting metal layer. A second superconducting metal is electroplated into the through silicon vias using the thermocompression bonded superconducting metal layer as a bottom electrode during the electroplating process, wherein the filling is from the bottom upwards.

## Claims

### Claim 1

A semiconductor structure comprising:
a thermocompression bonded superconducting metal layer sandwiched between a first silicon substrate and a second silicon substrate, wherein the first substrate includes a first portion of the superconducting metal layer, and the second substrate includes a second portion of the superconducting metal layer, wherein the second substrate comprises a plurality of through-silicon-vias to the thermocompression bonded superconducting metal layer, and wherein the superconducting metal layer surrounds each one of t through-silicon vias and is at a bottom surface of through-silicon vias to form a recess therein; and
an electroplated superconducting metal filling the plurality of through-silicon-vias.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the electroplated superconducting metal is different from the thermocompression bonded superconducting metal layer.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein the electroplated superconducting metal and the thermocompression bonded superconducting metal layer comprise aluminum, gallium, indium, lanthanum, molybdenum, niobium, rhenium, ruthenium, tin, tantalum, titanium, zinc, zirconium, or alloys thereof.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein the superconducting metal layer is at a thickness of about 20 nanometers to about 10 microns.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein the superconducting metal layer is at a thickness of about 20 nanometers to about 2000 nanometers.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein the superconducting metal layer is at a thickness of about 40 nanometers to about 1000 nanometers.

### Claim 7

A semiconductor structure comprising:
a thermocompression bonded superconducting metal layer sandwiched between a first silicon substrate and a second silicon substrate, wherein the second substrate comprises a plurality of through-silicon-vias to the thermocompression bonded superconducting metal layer, wherein the superconducting metal layer surrounds each one of the through-silicon vias and is at in bottom surface of the through-silicon to form a recess in the thermocompression superconducting metal layer.

### Claim 8 (depends on 7)

The semiconductor structure of claim 7, wherein the thermocompression bonded superconducting metal layer sandwiched between the first silicon substrate and the second silicon substrate comprises a first superconducting metal layer and a second superconducting layer, wherein the first and second superconducting metals are different.

### Claim 9 (depends on 7)

The semiconductor structure of claim 7, wherein the electroplated superconducting metal and the thermocompression bonded superconducting metal layer comprise aluminum, gallium, indium, lanthanum, molybdenum, niobium, rhenium, ruthenium, tin, tantalum, titanium, zinc, zirconium, or alloys thereof.

### Claim 10 (depends on 7)

The semiconductor structure of claim 7, wherein the superconducting metal layer is at a thickness of about 20 nanometers to about 10 microns.

### Claim 11 (depends on 7)

The semiconductor structure of claim 7, wherein the superconducting metal layer is at a thickness of about 20 nanometers to about 2000 nanometers.

### Claim 12 (depends on 7)

The semiconductor structure of claim 7, wherein the superconducting metal layer is at a thickness of about 40 nanometers to about 1000 nanometers.