# US 10,504,837 B2 · Semiconductor device including a conductive feature over an active region

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- Number: US 10,504,837 B2
- Document ID: US10504837B2
- Status: Granted
- Kind: B2
- Application number: 15/231,135
- Filed: 2016-08-08
- Published: 2016-11-24
- Granted: 2019-12-10
- Earliest claimed: 2014-10-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Tung-Heng Hsieh; Hui-Zhong Zhuang; Chung-Te Lin; Ting-Wei Chiang; Sheng-Hsiung Wang; Li-Chun Tien
- Web page: https://patentgrep.com/patent/US10504837B2

## CPC

- H10W 20/43: Layouts of interconnections
- H10D 64/01: Manufacture or treatment
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/8316: {the IGFETs characterised by having gate sidewall spacers specially adapted for integration}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0698: {Local interconnections}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a substrate having an active region, a first gate structure over a top surface of the substrate, a second gate structure over the top surface of the substrate, a pair of first spacers on each sidewall of the first gate structure, a pair of second spacers on each sidewall of the second gate structure, an insulating layer over at least the first gate structure, a first conductive feature over the active region and a second conductive feature over the substrate. Further, the second gate structure is adjacent to the first gate structure and a top surface of the first conductive feature is coplanar with a top surface of the second conductive feature.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate having an active region;
a first gate structure over a top surface of the substrate;
a second gate structure over the top surface of the substrate, wherein the second gate structure is adjacent to the first gate structure;
a pair of first spacers on each sidewall of the first gate structure;
a pair of second spacers on each sidewall of the second gate structure;
an insulating layer over the first gate structure;
a first conductive feature over the active region; and
a second conductive feature over the substrate, wherein a top surface of the first conductive feature is coplanar with a top surface of the second conductive feature and a top surface of the insulating layer over the first gate structure, the second conductive feature is over and physically contacting one spacer of the pair of first spacers.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising a third conductive feature, wherein the third conductive feature is over the first gate structure or the second gate structure.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first conductive feature has a tapered shape.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the second conductive feature has an L-shape or a U-shape.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein a portion of the second conductive feature is embedded in the first conductive feature.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the first conductive feature or the second conductive feature comprises tungsten.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the insulating layer comprises silicon nitride.

### Claim 8 (depends on 1)

The semiconductor device of claim 1 further comprising:
a source feature and a drain feature in the substrate, wherein the first gate structure is between the source feature and the drain feature, wherein the first conductive feature is over the source feature or the drain feature, and wherein a top surface of the first conductive feature is coplanar with a top surface of the insulating layer.

### Claim 9

A semiconductor device comprising:
a first gate structure over a substrate;
a second gate structure over the substrate;
an insulating layer over at least the first gate structure;
a first conductive feature over and contacting a top surface of the second gate structure, wherein a topmost surface of the first conductive feature is coplanar with a topmost surface of the insulating layer;
a second conductive feature over an active region of the substrate, wherein a portion of the first conductive feature is embedded in the second conductive feature, and wherein the topmost surface of the first conductive features is coplanar with a topmost surface of the second conductive feature;
a pair of first spacers on each sidewall of the first gate structure; and
a pair of second spacers on each sidewall of the second gate structure, the first conductive feature over and physically contacting one spacer of the pair of second spacers.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the insulating layer is between the pair of first spacers.

### Claim 11 (depends on 9)

The semiconductor device of claim 9 further comprising:
a third conductive feature over the first gate structure or the second gate structure.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, wherein the first conductive feature has an L-shape or a U-shape.

### Claim 13

A semiconductor device comprising:
a first gate structure and a second gate structure on a substrate;
an active region in the substrate, the active region being between the first and second gate structures;
a first insulating layer on the first gate structure and a second insulating layer on the second gate structure;
a pair of first spacers on each sidewall of the first gate structure and one of the pair of first spacers on a sidewall of the first insulating layer;
a pair of second spacers on each sidewall of the second gate structure and the second insulating layer;
a first conductive feature between the first and second gate structures, the first conductive feature over and electrically coupled to the active region;
a second conductive feature over at least the first gate structure, wherein a portion of a top surface of the second conductive feature is coplanar with a top surface of the second insulating layer over the second gate structure; and
a third conductive feature over the substrate, wherein a top surface of the first conductive feature is coplanar with a top surface of the third conductive feature and a top surface of the first insulating layer on the first gate structure.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, further comprising forming a fourth conductive feature, wherein the fourth conductive feature is over the first gate structure or the second gate structure.

### Claim 15 (depends on 13)

The semiconductor device of claim 13, wherein the second conductive feature has an L-shape or a U-shape.

### Claim 16 (depends on 13)

The semiconductor device of claim 13, wherein a portion of the second conductive feature is embedded in the first conductive feature.

### Claim 17 (depends on 2)

The semiconductor device of claim 2, wherein the first conductive feature has a tapered shape.

### Claim 18 (depends on 9)

The semiconductor device of claim 9, wherein the insulating layer comprises silicon nitride.

### Claim 19 (depends on 9)

The semiconductor device of claim 9, wherein the first conductive feature has a tapered shape.

### Claim 20 (depends on 9)

The semiconductor device of claim 9, wherein the first conductive feature or the second conductive feature comprises tungsten.