# US 10,504,836 B2 · Fan-out semiconductor package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,504,836 B2 - Document ID: US10504836B2 - Status: Granted - Kind: B2 - Application number: 16/053,193 - Filed: 2018-08-02 - Published: 2019-08-15 - Granted: 2019-12-10 - Earliest claimed: 2018-02-09 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Akihisa Kuroyanagi; Jun Woo Myung; Eun Sil Kim; Yeong A Kim - Web page: https://patentgrep.com/patent/US10504836B2 ## CPC - H10W 20/42: Vias, e.g. via plugs - H10W 20/43: Layouts of interconnections - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 72/30: Die-attach connectors - H10W 72/90: Bond pads, in general - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/095: {of vias therein} - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/635: {Through-vias} - H10W 70/655: Fan-out layouts - H10W 70/682: {comprising holes having chips therein} - H10W 70/685: comprising multiple insulating layers - H10W 72/073: {of die-attach connectors} - H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/874: {On different surfaces} - H10W 72/9413: {on encapsulations} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip disposed in the recess portion; a resin layer disposed on an active surface of the semiconductor chip; an encapsulant covering at least portions of side surfaces of the semiconductor chip and the resin layer and filling at least portions of the recess portion; a first redistribution layer disposed on the resin layer and the encapsulant; first redistribution vias penetrating through the resin layer to fill via holes in the resin layer exposing at least portions of the connection pads and electrically connecting the connection pads and the first redistribution layer to each other; and a connection member disposed on the resin layer and the encapsulant and including one or more second redistribution layers. ## Claims ### Claim 1 A fan-out semiconductor package comprising: a frame including a plurality of insulating layers, a plurality of wiring layers disposed on the plurality of insulating layers, and a plurality of connection via layers penetrating through the plurality of insulating layers and electrically connecting the plurality of wiring layers to each other, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip including a body having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface and a passivation layer disposed on the active surface and having openings exposing at least portions of the connection pads, and disposed in the recess portion so that the inactive surface is connected to the stopper layer; a resin layer disposed on the active surface of the semiconductor chip; an encapsulant covering at least portions of side surfaces of each of the semiconductor chip and the resin layer and filling at least portions of the recess portion; a first redistribution layer disposed on the resin layer and the encapsulant; first redistribution vias penetrating through the resin layer to fill via holes in the resin layer exposing at least portions of the connection pads and electrically connecting the connection pads and the first redistribution layer to each other; and a connection member disposed on the resin layer and the encapsulant and including one or more second redistribution layers electrically connected to the first redistribution layer, wherein the connection pads are electrically connected to the plurality of wiring layers. ### Claim 2 (depends on 1) The fan-out semiconductor package of claim 1, wherein an upper surface of the resin layer and an upper surface of the encapsulant are coplanar with each other. ### Claim 3 (depends on 2) The fan-out semiconductor package of claim 2, wherein an upper surface of an uppermost wiring layer of the plurality of wiring layers is coplanar with the upper surface of the resin layer and the upper surface of the encapsulant, and at least portions of the first redistribution layer are in physical contact with at least portions of the uppermost wiring layer of the plurality of wiring layers. ### Claim 4 (depends on 2) The fan-out semiconductor package of claim 2, wherein an upper surface of an uppermost connection via layer of the plurality of connection via layers is coplanar with the upper surface of the resin layer and the upper surface of the encapsulant, and at least portions of the first redistribution layer are in physical contact with at least portions of the uppermost connection via layer of the plurality of connection via layers. ### Claim 5 (depends on 1) The fan-out semiconductor package of claim 1, wherein the resin layer includes a photoimagable dielectric (PID). ### Claim 6 (depends on 1) The fan-out semiconductor package of claim 1, wherein the plurality of insulating layers include a core insulating layer, one or more first build-up insulating layers disposed on a lower surface of the core insulating layer, and one or more second build-up insulating layers disposed on an upper surface of the core insulating layer, and the core insulating layer has a thickness greater than that of each of the first and second build-up insulating layers. ### Claim 7 (depends on 6) The fan-out semiconductor package of claim 6, wherein the number of the first build-up insulating layers and the number of the second build-up insulating layers are the same as each other. ### Claim 8 (depends on 6) The fan-out semiconductor package of claim 6, wherein the recess portion penetrates through at least the core insulating layer and penetrates through at least one of the one or more first and second build-up insulating layers. ### Claim 9 (depends on 6) The fan-out semiconductor package of claim 6, wherein first connection vias penetrating through the first build-up insulating layer and second connection vias penetrating through the second build-up insulating layer are tapered in opposite directions to each other. ### Claim 10 (depends on 6) The fan-out semiconductor package of claim 6, wherein the recess portion does not penetrate through at least one of the first build-up insulating layers. ### Claim 11 (depends on 1) The fan-out semiconductor package of claim 1, wherein the stopper layer is a metal layer. ### Claim 12 (depends on 11) The fan-out semiconductor package of claim 11, wherein at least one of the plurality of wiring layers includes a ground, and the metal layer is electrically connected to the ground. ### Claim 13 (depends on 1) The fan-out semiconductor package of claim 1, wherein the inactive surface of the semiconductor chip is attached to the stopper layer through an adhesive member. ### Claim 14 (depends on 1) The fan-out semiconductor package of claim 1, wherein walls of the recess portion are tapered. ### Claim 15 (depends on 1) The fan-out semiconductor package of claim 1, wherein the stopper layer has a planar area greater than that of the inactive surface of the semiconductor chip. ### Claim 16 (depends on 1) The fan-out semiconductor package of claim 1, wherein the bottom surface of the recess portion has a planar area greater than that of the inactive surface of the semiconductor chip. ### Claim 17 (depends on 1) The fan-out semiconductor package of claim 1, wherein a region of the stopper layer exposed by the recess portion has a thickness smaller than that of an edge region of the stopper layer that is not exposed by the recess portion. ### Claim 18 (depends on 1) The fan-out semiconductor package of claim 1, wherein the edge region of the stopper layer that is not exposed by the recess portion is disposed between two of the plurality of insulating layers. ### Claim 19 (depends on 1) The fan-out semiconductor package of claim 1, further comprising: a first passivation layer disposed on the connection member and having openings exposing at least portions of an uppermost second redistribution layer of the second redistribution layers; underbump metal layers disposed in the openings of the first passivation layer and connected to at least portions of the exposed second redistribution layer; and electrical connection structures disposed on the first passivation layer and connected to the underbump metal layers. ### Claim 20 (depends on 1) The fan-out semiconductor package of claim 1, further comprising a second passivation layer disposed beneath the frame and having openings exposing at least portions of a lowermost wiring layer of the plurality of wiring layers.